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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-85ef3d768c8sm1519846a34.8.2026.11.04.01.08.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 01:08:10 -0800 (PST) From: Qiang Yu Date: Wed, 04 Nov 2026 01:08:01 -0800 Subject: [PATCH v4 2/3] phy: qcom: qmp-pcie: Add vdda-refgen supplies for Glymur X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261104-phyrefgen_1104-v4-2-ba508fc6ab40@oss.qualcomm.com> References: <20261104-phyrefgen_1104-v4-0-ba508fc6ab40@oss.qualcomm.com> In-Reply-To: <20261104-phyrefgen_1104-v4-0-ba508fc6ab40@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu , Manivannan Sadhasivam , Abel Vesa X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793783286; l=2038; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=X0zqKLQgxtFqsdr2c8NqWI9DTymrR5SFOBpbqURcmZU=; b=jOmVb1vGw8nEqcFE5bWnDz1WHLHxQTvffqHoM0iOlxKkPjMbu0qP+0COeDgjSm43OG0So7hmT x3ll492AqDnDr+4Py0zhLe3Smv3XmkxJ/2pgmb3yWL9VHEsYZvwRN7a X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA0MDAzNiBTYWx0ZWRfXzO/N5eu9nicB /TFFAT5LFdmU7OkVgZpDIcujY4b+HrDFxS7EdnL3yxwVhSPGCAOg4qYaS21Vk65fle0dLhqy6Zv 3ObSUuiy/hP8dT1Vv+b9/MaS10Rc7lM= X-Authority-Analysis: v=2.4 cv=OfINnRTY c=1 sm=1 tr=0 ts=6aeaf5fb cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=m2jQVEIWa0EwQwJFt7gA:9 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 X-Proofpoint-GUID: ll6yT8D0rKVBayfkItCDbUuwpflMdaLe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA0MDAzNiBTYWx0ZWRfX3Vp69a42ziYV rMkIKvnwSz/Ywbx1/y8elLk9bMqS4O8iHK4UY6hw5CqZThLXhFOg1Nrtaj8pvXIQ4BNcWwlgmx6 KuOvqked67eQ7piB+w1OKsqt9+WouRfB0Dxse+aBtgTPlJ3dJ75D/zqqdQniMnTQT4Ou2403pCO hOhSCnTBLhFVNbcVF8KiJDoCwmROiNPw3K5GGdNX4tgCe4QEGTD5amNcF9ACyE9E+sGAPNmywyr zDF6vA/jkA5FqBDu6MX61sRPx/D/gVco8BOZF83QMWPK6LysyMCp81UmfU+o2ZCuhf/Sd2Enn0h XSfMiUcX0xp/EH7pW6zPnLjoeujz9UW3r2uzUExUApjZVBgoIqfyvq2Tk9P8Z8ba0zqkG5E5ucT njndKGZKHAjuii6x4X7k8WlKnNGN6SFlD6nugePRvd6OvhH2yDuEqvlX5sdD9/6RlVhrf2AAd0g 953Dxfv7Q8MgwbEimZg== X-Proofpoint-ORIG-GUID: ll6yT8D0rKVBayfkItCDbUuwpflMdaLe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-04_02,2026-11-03_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 phishscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611040036 The refgen providing reference voltage for PCIe QMP PHY on Glymur requires two power supplies independent from the PHY's core and qref rails. Add support for vdda-refgen0p9 and vdda-refgen1p2 supplies with a dedicated glymur_qmp_phy_vreg_l list. Update both Gen5x4 and Gen4x2 configurations to use the new supply list. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 9cfabf474fd6..e226b65ec7c6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4106,6 +4106,10 @@ static const char * const sm8550_qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", "vdda-qref", }; +static const char * const glymur_qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", "vdda-refgen0p9", "vdda-refgen1p2", +}; + /* list of resets */ static const char * const ipq8074_pciephy_reset_l[] = { "phy", "common", @@ -5555,8 +5559,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = glymur_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(glymur_qmp_phy_vreg_l), .regs = pciephy_v8_50_regs_layout, @@ -5571,8 +5575,8 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = glymur_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(glymur_qmp_phy_vreg_l), .regs = pciephy_v8_regs_layout, -- 2.34.1