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Wed, 4 Nov 2026 07:21:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793776868; bh=3SZrotQFvmPueH/4BQAu3CKol44iMpmtrxjOSk9/PG0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To; b=JZ5x2YIpgS1YwbYgrJ+V+osRrvaQCxVZky/mrqXtvcJabvVcKINVIplojL0iDt1Xk K9q0lCaYaFFezEfoV3z7v1wfOtTAdzrK2eD8r6s/KQVoh7zkEBRp07Xy+asmJWEDaI liDm09gnSCcWthFOFYMVOITyS9DJ0y66qzrh+5PCk1yafP7kPcRnTzn1pGsKaABW4V +ySt92yE1jPpuSnO/sQY7Bgds0A34d/zkhfpFsOA9DQVvG6m4ceTv6G4els+cgNe1/ PnKccM87KhKDffMJVk8pfyCo4OtFW3/5FZ3yv/CT0djISJQZLFbh8nSD0ivA7ZIDUs lXwuM9VtLaFSA== Received: from nexus.subspace.kernel.org (localhost [IPv6:::1]) by lkml.kernel.org (Postfix) with ESMTP id C0BC046CFC; Wed, 4 Nov 2026 07:21:06 +0000 (UTC) From: Joseph Telaak via B4 Relay Date: Wed, 04 Nov 2026 02:21:00 -0500 Subject: [PATCH 3/4] dt-bindings: clock: Add Siflower SF19A2890 peripheral clock/reset managers X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-Id: <20261104-sf19a2890-sysm-v1-3-a4fac07df823@telaak.dev> References: <20261104-sf19a2890-sysm-v1-0-a4fac07df823@telaak.dev> In-Reply-To: <20261104-sf19a2890-sysm-v1-0-a4fac07df823@telaak.dev> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Chuanhong Guo , Yao Zi , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Joseph Telaak X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793776865; l=5702; i=joseph@telaak.dev; s=20261104; h=from:subject:message-id; bh=4KWzG/an7MCfsubmOaaiA9hvsylDSllSRf9ZeagAwwI=; b=BFngtlTXgARtrMOMTmNMZrMimkrw6si2n2L908ZtjYSDvyIC9x0TEz5kdqSKtHZ5h01j9OpCB qaJ4dn5BEwwD3CDGjlcaSN8pTt98x+RhwY4bxlvAOaKlqwLwslbMQwF X-Developer-Key: i=joseph@telaak.dev; a=ed25519; pk=oQI+UfddlZ0wK2ac4WKOGNjUl1ZEN8j9ZVFSqEDoNP0= X-Endpoint-Received: by B4 Relay for joseph@telaak.dev/20261104 with auth_id=1404 X-Original-From: Joseph Telaak Reply-To: joseph@telaak.dev Content-Transfer-Encoding: 7bit From: Joseph Telaak Each peripheral block of the Siflower SF19A2890 has a clock and reset manager of its own, with a reset register, a clock gate register and a bus output enable. The blocks differ in which gate and reset bits they use, so each has its own compatible, and clock N of a manager is its input clock N, gated. Based on Chuanhong Guo's binding, which described every block with one compatible and its bit layout in properties. Signed-off-by: Joseph Telaak --- .../clock/siflower,sf19a2890-periph-crm.yaml | 169 +++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/siflower,sf19a2890-periph-crm.yaml b/Documentation/devicetree/bindings/clock/siflower,sf19a2890-periph-crm.yaml new file mode 100644 index 000000000..7f0bce603 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/siflower,sf19a2890-periph-crm.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/siflower,sf19a2890-periph-crm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Siflower SF19A2890 peripheral clock and reset manager + +maintainers: + - Joseph Telaak + +description: | + Each peripheral, or group of peripherals, of the Siflower SF19A2890 has + a clock and reset manager of its own: a reset register, a clock gate + register, and a bus output enable that the peripherals need as well as + their clocks to answer bus requests. + + Clock N of the manager is input clock N, gated. The reset lines are: + + gmac-crm: 0 GMAC + usb-crm: 0 USB controller, 1 USB PHY power-on, 2 USB PHY + uart-crm: 0 UART0, 1 UART1, 2 UART2 + the others: 0 the block + +properties: + compatible: + enum: + - siflower,sf19a2890-gmac-crm + - siflower,sf19a2890-gpio-crm + - siflower,sf19a2890-i2c-crm + - siflower,sf19a2890-pwm-crm + - siflower,sf19a2890-rf-crm + - siflower,sf19a2890-spi-crm + - siflower,sf19a2890-timer-crm + - siflower,sf19a2890-uart-crm + - siflower,sf19a2890-usb-crm + - siflower,sf19a2890-wdt-crm + - siflower,sf19a2890-wlan24-crm + - siflower,sf19a2890-wlan5-crm + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: siflower,sf19a2890-gmac-crm + then: + properties: + clocks: + items: + - description: GMAC bus clock + - description: GMAC register clock + - description: RGMII transmit reference clock + - description: Timestamp unit clock + - if: + properties: + compatible: + contains: + enum: + - siflower,sf19a2890-wlan24-crm + - siflower,sf19a2890-wlan5-crm + then: + properties: + clocks: + items: + - description: AXI slave clock + - description: AXI master clock + - description: Radio platform clock + - if: + properties: + compatible: + contains: + const: siflower,sf19a2890-rf-crm + then: + properties: + clocks: + items: + - description: Test clock + - description: AXI slave clock + - description: Boot clock + - description: Low-power clock + - if: + properties: + compatible: + contains: + const: siflower,sf19a2890-usb-crm + then: + properties: + clocks: + items: + - description: USB controller clock + - description: AXI master clock + - description: USB PHY reference clock + - if: + properties: + compatible: + contains: + const: siflower,sf19a2890-spi-crm + then: + properties: + clocks: + items: + - description: APB clock + - description: SSP clock + - if: + properties: + compatible: + contains: + const: siflower,sf19a2890-uart-crm + then: + properties: + clocks: + items: + - description: UART0 APB clock + - description: UART1 APB clock + - description: UART2 APB clock + - description: UART0 clock + - description: UART1 clock + - description: UART2 clock + - if: + properties: + compatible: + contains: + enum: + - siflower,sf19a2890-gpio-crm + - siflower,sf19a2890-i2c-crm + - siflower,sf19a2890-pwm-crm + - siflower,sf19a2890-timer-crm + - siflower,sf19a2890-wdt-crm + then: + properties: + clocks: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + + clock-controller@19e24c00 { + compatible = "siflower,sf19a2890-uart-crm"; + reg = <0x19e24c00 0x10>; + clocks = <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_PBUS>, + <&clk CLK_MUXDIV_PBUS>, <&clk CLK_MUXDIV_UART>, + <&clk CLK_MUXDIV_UART>, <&clk CLK_MUXDIV_UART>; + #clock-cells = <1>; + #reset-cells = <1>; + }; -- Git-155)