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Tue, 03 Nov 2026 16:43:37 -0800 (PST) Received: from zippy.localdomain ([73.62.185.64]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4acea61f0c0sm513493fac.14.2026.11.03.16.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 16:43:37 -0800 (PST) From: Alex Elder To: sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, p.zabel@pengutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: daniel@riscstar.com, mohd.anwar@oss.qualcomm.com, lorenzo.bianconi@oss.qualcomm.com, fabrice.gasnier@foss.st.com, alexandre.torgue@foss.st.com, marex@nabladev.com, changhuang.liang@starfivetech.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: soc: introduce toshiba,tc9564-config-syscon.yaml Date: Tue, 3 Nov 2026 18:43:28 -0600 Message-ID: <20261104004332.2141282-2-elder@riscstar.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261104004332.2141282-1-elder@riscstar.com> References: <20261104004332.2141282-1-elder@riscstar.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Define the binding for the system controller that implements the clock and reset controller functionality present in the Toshiba TC9564 SoC. Co-developed-by: Daniel Thompson Signed-off-by: Daniel Thompson Signed-off-by: Alex Elder --- .../toshiba/toshiba,tc9564-config-syscon.yaml | 68 +++++++++++++++++++ MAINTAINERS | 8 +++ include/dt-bindings/soc/toshiba,tc9564.h | 46 +++++++++++++ 3 files changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/toshiba/toshiba,tc9564-config-syscon.yaml create mode 100644 include/dt-bindings/soc/toshiba,tc9564.h diff --git a/Documentation/devicetree/bindings/soc/toshiba/toshiba,tc9564-config-syscon.yaml b/Documentation/devicetree/bindings/soc/toshiba/toshiba,tc9564-config-syscon.yaml new file mode 100644 index 0000000000000..5a241a9c915d1 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/toshiba/toshiba,tc9564-config-syscon.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/toshiba/toshiba,tc9564-config-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba TC9564 Multifunction System Controller + +maintainers: + - Lorenzo Bianconi + - Alex Elder + - Daniel Thompson + +description: + The Toshiba TC9564 is an SoC accessed by a host system through the + upstream PCIe port on the PCIe switch it implements. The switch + includes an embedded PCIe endpoint that provides access to various + SoC peripherals via its BARs. These peripherals include a simple + controller to gate internal clocks, as well as a reset controller. + + The clock controller uses registers within the same page as a reset + controller, so this system controller controls access to both. + + A total of 21 simple gated clocks are implemented within the SoC. + At this time, support for enabling and disabling only a subset of + them is provided at this time. Similarly, the SoC implements 13 + resets, but currently not all of them can be controlled. + +properties: + compatible: + items: + - const: toshiba,tc9564-config-syscon + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + description: + Clock ids are defined in + + "#reset-cells": + const: 1 + description: + Reset ids are defined in + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + syscon@0 { + compatible = "toshiba,tc9564-config-syscon", "syscon"; + reg = <0x0 0x2000>; + clocks = <&tc9564_xo_board>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 93abbb315065d..2b1b29169e0e9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28339,6 +28339,14 @@ S: Maintained F: Documentation/devicetree/bindings/misc/pci1179,0220.yaml F: drivers/misc/tc9564-pci.c +TOSHIBA TC9564 SYSTEM CONTROLLER DRIVER +M: Lorenzo Bianconi +M: Alex Elder +M: Daniel Thompson +S: Maintained +F: Documentation/devicetree/bindings/soc/toshiba/toshiba,tc9564-config-syscon.yaml +F: include/dt-bindings/soc/toshiba,tc9564.h + TOSHIBA WMI HOTKEYS DRIVER M: Azael Avalos L: platform-driver-x86@vger.kernel.org diff --git a/include/dt-bindings/soc/toshiba,tc9564.h b/include/dt-bindings/soc/toshiba,tc9564.h new file mode 100644 index 0000000000000..66bcdf837f958 --- /dev/null +++ b/include/dt-bindings/soc/toshiba,tc9564.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +/* + * Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reserved. + */ + +#ifndef __SOC_TOSHIBA_TC9564_H__ +#define __SOC_TOSHIBA_TC9564_H__ + +/* Clock IDs */ + +#define CLOCK_PLL 0 + +#define CLOCK_62_5M 1 +#define CLOCK_125M 2 +#define CLOCK_250M 3 +#define CLOCK_312_5M 4 + +#define CLOCK_MSIGEN 5 + +#define CLOCK_MAC0_TX 6 +#define CLOCK_MAC0_RX 7 +#define CLOCK_MAC0_125M 8 +#define CLOCK_MAC0_312_5M 9 +#define CLOCK_MAC0_ALL 10 + +#define CLOCK_MAC1_TX 11 +#define CLOCK_MAC1_RX 12 +#define CLOCK_MAC1_125M 13 +#define CLOCK_MAC1_312_5M 14 +#define CLOCK_MAC1_ALL 15 +#define CLOCK_MAC1_RMII 16 + +/* Reset IDs */ + +#define RESET_MSIGEN 0 + +#define RESET_MAC0_MAC 1 +#define RESET_MAC0_PMA 2 +#define RESET_MAC0_XPCS 3 + +#define RESET_MAC1_MAC 4 +#define RESET_MAC1_PMA 5 +#define RESET_MAC1_XPCS 6 + +#endif /* __SOC_TOSHIBA_TC9564_H__*/ -- 2.53.0