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Peter Anvin" , Mario Limonciello , Yazen Ghannam CC: , Ariadne Conill , Sean Christopherson , Juergen Gross , Jason Andryuk , , Ingo Molnar , Subject: [PATCH] x86/CPU/AMD: Don't print reset reason in VMs Date: Tue, 3 Nov 2026 20:30:25 -0500 Message-ID: <20261104013026.185392-1-jason.andryuk@amd.com> X-Mailer: git-send-email 2.34.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000010:EE_|CH1PR12MB9600:EE_ X-MS-Office365-Filtering-Correlation-Id: b4ef121e-7884-49d3-90fd-08df3a13394f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|23010399003|260925022911599003|18002099003|260925021311599003|260925021911599003|261102123227099003|56012099006|10067099003|261009223027099003|261022105027099003|261021121427099003|261021123027099003|5023799004|11063799006|261028144727099003|261026121527099003|261026140227099003; X-Microsoft-Antispam-Message-Info: jswD/zhYDvaAX6T7oc88dlTbW69uUHve8rVrdA/duX9Rk8HzotcVPQ/2mztIehNEJykfecovpzNMNm66evQX2RqYDz5v70ekyhu0tvs7n77rhaK5b+uK+PSJci5PFL7x6K+5tD+abqAk+SVnP6FqKOCbkD1LsnQxO09R3/5nCnkb3gzISrJdhsMxNDFU71XalucSirXoYdVBcGWrIun4/PyUKbXhQRjtQ3PfJeGQ8pw5sAUIRpVY7hBh0q67WTCiyEPNQUf7ektlhIjrusKytZ0DvqbyiVJEYDszQ+A/0zK/Can112A8+vK/gFoiMt3+8gUwIJH6omYsRd1gIO+mhMFEkkef+BTZKseQAR8mJcqn6x42atOK5B4W6z4zIe31LY7s4JtMK6XlnvAQEpdpX6ducO7f+g9g/jrxfNY/ctuwgKO32NZNAfdfWxDaIaJllkOBjS+054yBauFRQ3cWQGuRDKuvVkqxVm5lAwXYblBFhbvW/NVfp3r4QbT1vfIC8pC4Hcgg8lIXQMq1ySQKmXwVhWsQXsFAcnXQBSUvq2/r68qH3kWOj/oOsUUob1wdaUBxaN3XDhmBov9Lce6q/M4NSqFyNVIBvGHiT5ybFyMLUmbJkTN1V3XsIMuASIcNMGFRxgr8zc9Cy0FEETAJiIO9ggH4jMMYgZ9Aui1IWRe1U06mfe1WtAqJWBO/xvYt3q56rsoklb2+w1GPig7K1w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700016)(23010399003)(260925022911599003)(18002099003)(260925021311599003)(260925021911599003)(261102123227099003)(56012099006)(10067099003)(261009223027099003)(261022105027099003)(261021121427099003)(261021123027099003)(5023799004)(11063799006)(261028144727099003)(261026121527099003)(261026140227099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OjS/bccuQx9CI8q/cnb9g62Faud4TSmnaxBwSmUzvSC1q/TMf1wZ4OkFAnyn72KPYCJHVArTRUm+RMzjqvgjkvyIpnuYMggmWPOhHB0JhVk6NwzpB/3zNGu2A9Ev/x6DF6JGUQRJ/VAiFrmXFu7UquRlE//OMbPGBlnP3Xox25x7rl6jLowngiIIyZnXq53zWUIZwOsKyTCuxHWz8JXzEsBfL63gGCNX6MYHvDcQO45MR31O0ppGlIhi+RDfLer6n3sZsfJ8vX9czrQXOoRd7lbJcbUMEoRVtBjkjrsMsqjkng77m5OKocDUzhqjQxkEVv9qck0XKJGcIgvMMnb4AO+1e9hwu977rk7jJwud3rlZAbM8XZvShvJHZgwkv2r2kU/tWYIE0lVP6SeemlVwVTJU5XvlZScZg+ea9VR/PoYpVDbL5pNhfHsL7PCMxWZ5 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 01:30:34.9625 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b4ef121e-7884-49d3-90fd-08df3a13394f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000010.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9600 print_s5_reset_status_mmio() expects to read FCH MMIO on baremetal. VMs don't have emulated FCH registers, so there is nothing to check. Add an early exit when running on a hypervisor. The real motivation is Xen PV domUs can't boot on Zen CPUs. PV domUs PTE contain system physical addresses - they don't have concept of guest physical addresses. domUs can only map physical addresses they are assigned, so a domU fails to map the FCH MMIO addresses. However set_pte() does not return failure, so ioremap() returns a pointer while the PTEs are unpopulated. print_s5_reset_status_mmio() faults when reading through the pointer, breaking the boot. This change fixes Xen PV domUs booting on Zen CPUs. dom0 can map the FCH MMIO, but it has X86_FEATURE_HYPERVISOR set. With this change, it no longer prints the reset reason. Fixes: ab8131028710 ("x86/CPU/AMD: Print the reason for the last reset") Cc: stable@vger.kernel.org Suggested-by: Borislav Petkov Signed-off-by: Jason Andryuk --- dom0 could work, but that would require a xen_initial_domain() check. I've wondered about a different approach: We can't directly check for a device for the FCH_PM_BASE memory, but maybe we could check for a PCI ISA Bridge with PCI_VENDOR_ID_AMD. That might be close enough to indicate real hardware? But it would still be a heuristic, so I'm not sure how much better that would be. --- arch/x86/kernel/cpu/amd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 40463bad1078..580ccc2ce5fc 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1357,7 +1357,8 @@ static __init int print_s5_reset_status_mmio(void) u32 value; int i; - if (!cpu_feature_enabled(X86_FEATURE_ZEN)) + if (!cpu_feature_enabled(X86_FEATURE_ZEN) || + cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) return 0; addr = ioremap(FCH_PM_BASE + FCH_PM_S5_RESET_STATUS, sizeof(value)); -- 2.34.1