From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=74.125.82.180 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793761317; b=vCZc94Te/G9lozFew5/67WyJdrmaZiSxq39YSIMbfEgBCNUxzUhKoYeHMOcfCaqoGmjt Yv2bwWlBhqXBKyvxv+TR/0caURN1aBTFV9pSaTuHqG1iztTKqpCD7Vf70HpSRieJ+fw2J /cYc6FlRNk7QngcxzjlbqqZS3mQIGpJo9q50xnEWlac/SGmejauhVzS9UGWfMLoROVBKL Vatbr7CVFR8T+XYSb+YtWtrO9ZWteGmrOB5Ypshgqh73FzpHfGS22Q/Ftf+5BCp7nqvxz v5AXjViHipssnm3UQsN5W1UD+dUH948waLbvdTZOJfWfmYHCM6LN+spsKDQWvNe7WSg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793761317; h=DMARC-Filter:Received:DKIM-Signature:X-Google-DKIM-Signature: X-Forwarded-Encrypted:X-Gm-Message-State:X-Gm-Gg:X-Received:Received: From:To:Cc:Subject:Date:Message-Id:X-Mailer:MIME-Version: Content-Transfer-Encoding; bh=YlterDeN6T+DiNtjdG/tEDnVKD1WZhlw9rJO8gzsf8k=; b=BoowLUuJ7NPaRKPW6W/v7kLKwtAJVBA92eqhOi7KMyAIjar6tQU4ojg4yrFcS8/Z4It4 gGJrwwR9dZLQMxzO7HcFYYPc1H0HOBJm7Z+cqIAh0HIr/4pFO74rf1vESmUzlSfLbjxT8 +qamTUELyLu4vUIWIJQsEgJbQkoR/PTwrjSI7e1P2v9MadfA4DcWKDe5mOG8JmNywudgE 7Ntaut0cqHPmVnlledGdvDlA8Oo22/s3YpcpkOML5p7KjLzOycUewhdk0FgX5e3PaVco3 abuaY8F39GZH/QPSrpXtHfxOLhs8LE/ZM+pmPfbiv3bAek5kLH2Z+zYP8wVJ8DUxXnA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20260707 header.b=RIep7yVw; arc=none smtp.remote-ip=74.125.82.180 Received: from mail-dy1-f180.google.com (mail-dy1-f180.google.com [74.125.82.180]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D058606A32D for ; Wed, 4 Nov 2026 03:01:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 1D058606A32D Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20260707 header.b=RIep7yVw Received: by mail-dy1-f180.google.com with SMTP id 5a478bee46e88-3514b90bb89so409270eec.1 for ; Tue, 03 Nov 2026 19:01:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20260707; t=1793761315; x=1794366115; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to:content-type; bh=YlterDeN6T+DiNtjdG/tEDnVKD1WZhlw9rJO8gzsf8k=; b=RIep7yVwoDzeBBxgcbtGvwlWBpSX5H1e2N2jeaBtOEl6VxNxmOiZmizOCCtWQC0JIE IuoP/hp4Gnb2kmcoZ/wFoHDoyEBvzHClcePOKyOxhypKzd035JTLc3Wf83BdO9XP+1Ye L1Jpnaxbgb7gjNgN7fGBJiRKdbCx17YOmp6JQb3wj/UK75EJaMJ5J1AWrexy9/14u4m+ Gcy/xGPuXx5ZRA95ELCAL99ndeTPdkM7ka93/x/agtvz0NhWnogLby3KuV9azjVB145c JLaQZ/2Qd4PVUE/5R3LcV8oWMBlU1XU9Cmp1duo7kiDQOvlbiv4hC1kJylHCmunDQFYo EARQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1793761315; x=1794366115; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=YlterDeN6T+DiNtjdG/tEDnVKD1WZhlw9rJO8gzsf8k=; b=StJWijFrnLhfIyFkKrQnDFMNRLjQUMRc5jziUbg7UAwei60ZQgc+YqzoJud2Tm3bHO V5IvDjsaoHXHndcYWfu4xu5OTu/2DAa7ZoUdFfXcqePj1cCeMDtNvbBk0eeb0R3SU/WS B51ME/YjSwEnYRkUP2okuv5pyYWgApXSNPGLjCHOgOA6a+X3b4IwbYoXhry+6KPd43Dm m+QrCaxcQkuEOf4koSyujRif05JSajyH0qM2YANTngdOSPk+SALp8nTbsIj9haZLaltJ MlHfKLdQ3BNMAw7M7APoTUkPPYwjuGjV/Wn0Q1iSi7SkWYnlavaOS0Dl/bYeXBtPKAq8 2ITw== X-Forwarded-Encrypted: i=1; AKwUvByejFR1rx2pfT8iZSfqK5GC9Y9+NnniArGIIp0+sK9l8fNBT1aag+aMQxdFkbOYqAGYKakobSEEmL1TQOI=@vger.kernel.org X-Gm-Message-State: APuU4Z9g2/N2bMXbgb5iEb4U2kd4Cuw/I7g0vw+2qCU7jscC2zup7r2a ntUf8qMFYCToiD/ceD1FRBXPR1S9wAF6EIUdH7r2QtCWKOPQhk1LPnnk X-Gm-Gg: AYBFou2ilkLPU/u79aQ7mbEHix7clOA+HJRzSRtWoG/D5/shSYP4FtT1DJx/wpoZMa2 zUf0U0c3a6iHZWVFEocHoR0h+SqnR0FwCzlGJdzJuqDma6CF7aLOnBS3IulqNi8UUkVnTT8t6Bk bQuadHB44veEL/hpUd/fZEmmwrjk4/xprTd4vCQh0yLzDWtNLfRH93EqykhySBr53Rbe4XMh6B0 AAHoCJc6U6h3IQ5bimLDTzFt6RxuEUIgrLcbuTmaXozAOrZ4ClLoT80YvO4xPjZlqTXigiHN3Fh oDKRwhhZu6Wire7ePfOeX8DXzA1dN3Ljc11af7zkAds13lGmhwO0Kx0N5MgFNIWnI0pMKd4O0QT 6iyjenxM8iGVjm7V1vsbpFvuhPHV9j52bXBoNZcY9uJJqClXQsho1ddrJD8KoOZcNcNRAlc3MnJ ULwFYn4gPVWvgL7hj0FVKkiUNTZAyGAk99Dc3P0khzfWr5XDkWsO56COZEzqKfFUxkI1YsB2UyP vUo8WucOJSw29beYla5WWpSV+yfNWYf/wk9X2yJCgkYt632itLW1UtgO4YX99jcBE8tcf5sSpkE 5q9lnCa2nHSf36dUwBiaJLlMzkmJULkPvo8B8kWQ/ziJE50ABlaW4Uw= X-Received: by 2002:a05:7300:8813:b0:36c:49a7:86ac with SMTP id 5a478bee46e88-36c49a78c8cmr4600001eec.37.1793761314951; Tue, 03 Nov 2026 19:01:54 -0800 (PST) Received: from arm-a100.. ([140.112.28.118]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36ca392abe4sm2951819eec.19.2026.11.03.19.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 19:01:54 -0800 (PST) From: Tzu-Ching Yang To: Thomas Bogendoerfer Cc: "Maciej W. Rozycki" , Marco Crivellari , Frederic Weisbecker , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-mips@vger.kernel.org, llvm@lists.linux.dev, linux-kernel@vger.kernel.org, kernel test robot , stable@vger.kernel.org Subject: [PATCH] MIPS: Fix genex.S build with LLVM before 21 Date: Wed, 4 Nov 2026 11:01:47 +0800 Message-Id: <20261104030147.3117325-1-shingekinocore@gmail.com> X-Mailer: git-send-email 2.34.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since commit 56651128e2fb ("MIPS: Fix idle VS timer enqueue"), BUILD_SKIPOVER_PROLOGUE uses label differences as the immediates of ORI and PTR_ADDIU. The LLVM integrated assembler accepts such an immediate only from LLVM 21 on, so LLVM=1 builds of every MIPS configuration fail with LLVM 17 to 20 unless LLVM_IAS=0 is set: :7:11: error: expected an immediate ori $26, r4k_wait_idle_size - 2 ^ :10:14: error: expected an immediate addiu $26, r4k_wait_exit - r4k_wait_insn + 2 ^ Wrap both expressions in %lo(). For that operator, LLVM 17 to 20 emit a LO16 fixup instead of rejecting the operand, and resolve it when writing the object, since both expressions are constants by then; no relocation is left. Both values are between 2 and 30, so %lo() does not change them. GNU as and LLVM 21 to 23 emit the same code as before, except on microMIPS, where GNU as now uses the 32-bit ADDIU in the delay slot instead of the 16-bit one. With GCC, the 2 extra bytes replace the 16-bit NOP that padded the end of the prologue, so all symbols keep their addresses; with Clang and LLVM_IAS=0, except_vec_vi and the code after it, up to nmi_handler, move by 4 bytes. Fixes: 56651128e2fb ("MIPS: Fix idle VS timer enqueue") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202505071331.Z0N2eSkr-lkp@intel.com/ Link: https://github.com/llvm/llvm-project/commit/b65e0947cade9bd39036a7700b54c1df4ec00756 Cc: stable@vger.kernel.org # 6.18.x: 2b6d718c8dbe: MIPS: Fix whitespace damage in r4k_wait from VS timer fix Cc: stable@vger.kernel.org # 6.18.x Signed-off-by: Tzu-Ching Yang --- No MIPS hardware here. Against mips-fixes (v7.4-rc1). All builds use W=1 and kernel.org toolchains. - genex.o, before and after, with GCC 8.1 to 16.2 and with LLVM 17 to 23, both with the integrated assembler and with LLVM_IAS=0. Configs: 64r6el, 32r6el, 64r2el, 32r2el, eyeq5, eyeq6, malta (little and big endian, MIPS32r1, microMIPS little and big endian), ip22, ip27, loongson3 and cavium_octeon. - The objects are byte-identical before and after with GCC, with LLVM_IAS=0 and with LLVM 21 to 23. The only exception is the microMIPS ADDIU above. The 4-byte move with LLVM_IAS=0 is harmless: set_vi_handler() computes the offsets and the length of the vectored handler from symbols before copying it, and ejtag_debug_handler and nmi_handler are only referenced through their symbols. - LLVM 17 to 20 now assemble genex.o for all of these configs except microMIPS and Octeon, which the integrated assembler rejects for other reasons. For malta (little and big endian, MIPS32r1), ip22 and ip27, these objects are byte-identical to the LLVM 21 genex.o. - vmlinux of 64r2el, 32r2el and malta, built with GCC 8.1 and 16.2, LLVM 17, 20, 21 and 23, and LLVM 17 with LLVM_IAS=0. Where both sides build, vmlinux is byte-identical before and after. With LLVM 17 and 20, genex.o was the only object that failed before, and vmlinux links after. No new warnings. - The malta kernels built with GCC 8.1 and 16.2, LLVM 17, 20 and 23, and LLVM 17 with LLVM_IAS=0 boot under QEMU 6.2 -cpu 24Kf. That CPU uses r4k_wait(), so interrupts go through skipover_handle_int. Each kernel boots to an init that keeps the CPU going in and out of idle and then reboots; a QEMU trace shows every interrupt that lands in the idle region resuming at r4k_wait_exit. A microMIPS kernel does not boot under QEMU -cpu M14Kc with or without this patch, so the microMIPS change was not run. In the 2025 thread [2], Nathan suggested requiring LLVM 21 for MIPS in min-tool-version.sh, and Maciej an #error for older Clang. Both would also stop LLVM 17 to 20 builds with LLVM_IAS=0, which work today, and the stable trees would need the same change before 56651128e2fb could go back to them. On 6.18.y, which also allows LLVM 15 and 16, the patch applies after 2b6d718c8dbe, and LLVM 15 and 16 fail and are fixed the same way. The 56651128e2fb backport was dropped from the 6.14, 6.12 and 6.6 stable queues because of this build failure [1], so 6.12.y and 6.6.y still lack that fix. [1] https://lore.kernel.org/r/2025051415-unloader-likely-b0e6@gregkh/ [2] https://lore.kernel.org/r/20250521224450.GA2412476@ax162/ arch/mips/kernel/genex.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index be1b049d856f..ef27965f6ad9 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -146,10 +146,10 @@ r4k_wait_exit: MFC0 k0, CP0_EPC /* Subtract/add 2 to let the ISA bit propagate through the mask. */ PTR_LA k1, r4k_wait_insn - 2 - ori k0, r4k_wait_idle_size - 2 + ori k0, %lo(r4k_wait_idle_size - 2) /* %lo() for LLVM < 21 */ .set noreorder bne k0, k1, \handler - PTR_ADDIU k0, r4k_wait_exit - r4k_wait_insn + 2 + PTR_ADDIU k0, %lo(r4k_wait_exit - r4k_wait_insn + 2) /* ditto */ .set reorder MTC0 k0, CP0_EPC .set pop base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.34.1