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Tue, 03 Nov 2026 21:59:04 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b07c9928c4sm7840110a91.15.2026.11.03.21.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 21:59:04 -0800 (PST) From: Rosen Penev To: linux-mips@vger.kernel.org, Thomas Bogendoerfer , Stephen Boyd Cc: Brian Masney , Jerome Brunet , Alban Bedel , Antony Pavlov , linux-kernel@vger.kernel.org (open list), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK) Subject: [PATCH 7/8] clk: ath79: give each compatible its own init function Date: Tue, 3 Nov 2026 21:58:51 -0800 Message-ID: <20261104055852.152340-8-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261104055852.152340-1-rosenp@gmail.com> References: <20261104055852.152340-1-rosenp@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Every compatible already has its own CLK_OF_DECLARE(), yet they all shared one init function, which then matched the compatible again to pick the SoC code. Have each CLK_OF_DECLARE() call a small wrapper that passes the SoC init function to the common code instead. Signed-off-by: Rosen Penev --- drivers/clk/clk-ath79.c | 72 +++++++++++++++++++++++++++-------------- 1 file changed, 47 insertions(+), 25 deletions(-) diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c index 768c9e410b59..8086b4f6378c 100644 --- a/drivers/clk/clk-ath79.c +++ b/drivers/clk/clk-ath79.c @@ -504,11 +504,12 @@ static int __init qca956x_clocks_init(void __iomem *pll_base) return ath79_set_clks(cpu_rate, ddr_rate, ahb_rate); } -static void __init ath79_clocks_init_dt(struct device_node *np) +static void __init ath79_clocks_init_dt(struct device_node *np, + int (*soc_init)(void __iomem *pll_base)) { struct clk *ref_clk; void __iomem *pll_base; - int ret = -ENODEV; + int ret; clk_data = kzalloc_flex(*clk_data, hws, ATH79_CLK_END); if (!clk_data) @@ -534,21 +535,7 @@ static void __init ath79_clocks_init_dt(struct device_node *np) goto err_clk; } - if (of_device_is_compatible(np, "qca,ar7100-pll")) - ret = ar71xx_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,ar7240-pll") || - of_device_is_compatible(np, "qca,ar9130-pll")) - ret = ar724x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,ar9330-pll")) - ret = ar933x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,ar9340-pll")) - ret = ar934x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,qca9530-pll")) - ret = qca953x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,qca9550-pll")) - ret = qca955x_clocks_init(pll_base); - else if (of_device_is_compatible(np, "qca,qca9560-pll")) - ret = qca956x_clocks_init(pll_base); + ret = soc_init(pll_base); /* the rates are fixed, so the registers aren't needed any more */ iounmap(pll_base); @@ -578,11 +565,46 @@ static void __init ath79_clocks_init_dt(struct device_node *np) clk_data = NULL; } -CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt); -CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt); -CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt); -CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt); -CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt); -CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt); -CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt); -CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt); +static void __init ar71xx_clocks_init_dt(struct device_node *np) +{ + ath79_clocks_init_dt(np, ar71xx_clocks_init); +} + +static void __init ar724x_clocks_init_dt(struct device_node *np) +{ + ath79_clocks_init_dt(np, ar724x_clocks_init); +} + +static void __init ar933x_clocks_init_dt(struct device_node *np) +{ + ath79_clocks_init_dt(np, ar933x_clocks_init); +} + +static void __init ar934x_clocks_init_dt(struct device_node *np) +{ + ath79_clocks_init_dt(np, ar934x_clocks_init); +} + +static void __init qca953x_clocks_init_dt(struct device_node *np) +{ + ath79_clocks_init_dt(np, qca953x_clocks_init); +} + +static void __init qca955x_clocks_init_dt(struct device_node *np) +{ + ath79_clocks_init_dt(np, qca955x_clocks_init); +} + +static void __init qca956x_clocks_init_dt(struct device_node *np) +{ + ath79_clocks_init_dt(np, qca956x_clocks_init); +} + +CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ar71xx_clocks_init_dt); +CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ar724x_clocks_init_dt); +CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ar724x_clocks_init_dt); +CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ar933x_clocks_init_dt); +CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ar934x_clocks_init_dt); +CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", qca953x_clocks_init_dt); +CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", qca955x_clocks_init_dt); +CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", qca956x_clocks_init_dt); -- 2.56.0