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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: P56w94WRtsdWtReMxzv9NnFlrnKRdmDSD94OGbDr7bNz224KZhx2ZyPP6Jm3ZOmvXmMXJZaAGEIQ5AviF9YiCoxPI7TyWH7Ks3CoJuXroRDiT64WZk8+H9CKioJPUAdXK9E/S+lUS6S1kd9wuAE9euV9/dF8Qr06ngil69vZYu7KzdsSap6XbBTvBIC5ylt/UcSFfLNp4SuJ7MOM5GKqZO5BUyfNdXhV8HhNL+4ZWEunpm2+Dc2InON52QCJBMqq9CWILe9vNqiR4BQyk1wZ0NZYNEtpPKEjErVL94p98FxXSeJ8jRH4wxdIYkWQ3fqMtYm0fKb9ODSFXcPvGIjxgeE01vYdDFtMxuL51T79pQyRx8fWr2zLiARvnmOU/o3gJhiw/fOn2jFjURTIAQDtZ7Jwo5b5Qkx49wmNSi5TKTMNXurZ4N2uANTw5h64xfpJ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 11:10:16.9751 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c70bf4c3-4d9e-458c-a865-08df3a643505 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: PH3PEPF0005961A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8402 Tegra268 reuses the Tegra264 ADMA register layout but has ten DMA channels, five request IDs, six pages and a different uniform FIFO size. Add its binding and SoC data, and derive the shared page configuration masks from these limits. Make the Tegra264 FIFO size explicit first so Tegra268 can select its FIFO size without changing the existing devices' FIFO programming. Anupama Kunkulagunta (2): dt-bindings: dma: nvidia,tegra210-adma: Add Tegra268 support dmaengine: tegra210-adma: Add Tegra268 support Sheetal (1): dmaengine: tegra210-adma: Make Tegra264 FIFO size explicit .../bindings/dma/nvidia,tegra210-adma.yaml | 13 ++++ drivers/dma/tegra210-adma.c | 73 +++++++++++++++---- 2 files changed, 73 insertions(+), 13 deletions(-) -- 2.43.0