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Wed, 4 Nov 2026 03:10:03 -0800 Received: from build-sheetal-noble-20261014.internal (10.127.8.14) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Wed, 4 Nov 2026 03:10:03 -0800 From: Sheetal To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Frank Li , Laxman Dewangan , Jonathan Hunter , Thierry Reding , Mohan Kumar , Sameer Pujar , , , , , Anupama Kunkulagunta , Sheetal Subject: [PATCH 3/3] dmaengine: tegra210-adma: Add Tegra268 support Date: Wed, 4 Nov 2026 11:09:32 +0000 Message-ID: <20261104110932.1097294-4-sheetal@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261104110932.1097294-1-sheetal@nvidia.com> References: <20261104110932.1097294-1-sheetal@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH01EPF000BE940:EE_|PH0PR12MB7862:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d91bec8-f6bc-4b47-aa64-08df3a643651 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|23010399003|1800799024|6133799003|10067099003|18002099003|22082099003|56012099006|11063799006|261102123227099003|261022113327099003|261022075727099003|261022105027099003|261026121527099003|261026140227099003|261028144727099003|261021123027099003|261021121427099003|261009223027099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qFnhzs8W3d2AVLMkvrD1Xnzo4NMZOuy8occIBIxt3rDhhcg6udBm53xKcQcZLsGSzt9cwYFxyBT8i+66vRkn9UFjhtBae/AoLTU3aZmyEmUC69eb69mpzQUGbFoSbLHhpEUno7RdQ8mYGwX7hz32/yYPaaPfzctaUwQEJiW23c2lbcIVgeDr8CcT3N2kH/q/DzYOZzfvKTNHDPy7I7lJBbkw2SPyEZAjyo3PqHp405WRDU8azwPiUrAXnw4/0rGo6NOqJEW2FY3EexVoy4eAdBV2exFa2jLUrxXWhmaJKCqWDkfIXFN5nxSC45J9C8irRiB13STFm8bV36x8f8SNiwE0s6TNjeunVNm0mB3kVIezhmJOmV3ihwHrMLuXtOVm6/bTYec0/Or4YsZS/ULXFV/6pa0Pe+FIey/H00+dSUUGmWQRvmNl4Nsw1Nsq4MLE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 11:10:19.1129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d91bec8-f6bc-4b47-aa64-08df3a643651 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH01EPF000BE940.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7862 From: Anupama Kunkulagunta Tegra268 has 10 bidirectional ADMA channels to support the five RX and five TX ADMA interfaces exposed by the audio processing engine (APE). Only DMA request IDs 1 through 5 are valid for this device. Set nr_channels to 10 and ch_req_max to 5 to match these limits. Reuse the Tegra264 register layout and page configuration helper. Derive the channel and request masks from the SoC data so the helper handles both devices while preserving the existing Tegra264 register values. Keep request bit 0 set, as in the Tegra264 programming. Add the Tegra268 compatible and SoC data, including its six ADMA pages and uniform FIFO size. Signed-off-by: Anupama Kunkulagunta Signed-off-by: Sheetal --- drivers/dma/tegra210-adma.c | 49 +++++++++++++++++++++++++++++++------ 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 293a1119e07a..2d9dd41141cd 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -5,6 +5,7 @@ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include @@ -279,6 +280,8 @@ static void tegra186_adma_global_page_config(struct tegra_adma *tdma) static void tegra264_adma_global_page_config(struct tegra_adma *tdma) { u32 global_page_offset = tdma->ch_page_no * TEGRA264_ADMA_GLOBAL_PAGE_OFFSET; + u64 ch_mask = GENMASK_ULL(tdma->cdata->nr_channels - 1, 0); + u64 req_mask = GENMASK_ULL(tdma->cdata->ch_req_max, 0); /* If the default page (page1) is not used, then clear page1 registers */ if (tdma->ch_page_no) { @@ -291,12 +294,18 @@ static void tegra264_adma_global_page_config(struct tegra_adma *tdma) } /* Program global registers for selected page */ - tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 + global_page_offset, 0xffffffff); - tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 + global_page_offset, 0xffffffff); - tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 + global_page_offset, 0xffffffff); - tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 + global_page_offset, 0x1); - tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 + global_page_offset, 0xffffffff); - tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 + global_page_offset, 0x1); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 + global_page_offset, + lower_32_bits(ch_mask)); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 + global_page_offset, + upper_32_bits(ch_mask)); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 + global_page_offset, + lower_32_bits(req_mask)); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 + global_page_offset, + upper_32_bits(req_mask)); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 + global_page_offset, + lower_32_bits(req_mask)); + tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 + global_page_offset, + upper_32_bits(req_mask)); } static int tegra_adma_init(struct tegra_adma *tdma) @@ -727,7 +736,7 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, * * ADMA FIFO size is set as per below (based on default ADMAIF channel * FIFO sizes): - * For Tegra264: + * For Tegra264 and Tegra268: * fifo_size = ch_fifo_size * For devices prior to Tegra264: * fifo_size = 0x2 (sreq_index > sreq_index_offset) @@ -1035,10 +1044,36 @@ static const struct tegra_adma_chip_data tegra264_chip_data = { .set_global_pg_config = tegra264_adma_global_page_config, }; +static const struct tegra_adma_chip_data tegra268_chip_data = { + .adma_get_burst_config = tegra186_adma_get_burst_config, + .global_reg_offset = 0, + .global_int_clear = 0x800c, + .global_ch_fifo_base = ADMA_GLOBAL_CH_FIFO_CTRL, + .global_ch_config_base = ADMA_GLOBAL_CH_CONFIG, + .ch_req_tx_shift = 26, + .ch_req_rx_shift = 20, + .ch_dir_shift = 10, + .ch_mode_shift = 7, + .ch_base_offset = 0x10000, + .ch_tc_offset_diff = 4, + .ch_config = ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(1) | + ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(8), + .ch_req_mask = 0x3f, + .ch_dir_mask = 7, + .ch_req_max = 5, + .ch_reg_size = 0x100, + .nr_channels = 10, + .ch_fifo_size_mask = 0x7f, + .ch_fifo_size = 5, + .max_page = 6, + .set_global_pg_config = tegra264_adma_global_page_config, +}; + static const struct of_device_id tegra_adma_of_match[] = { { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data }, { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data }, { .compatible = "nvidia,tegra264-adma", .data = &tegra264_chip_data }, + { .compatible = "nvidia,tegra268-adma", .data = &tegra268_chip_data }, { }, }; MODULE_DEVICE_TABLE(of, tegra_adma_of_match); -- 2.43.0