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When it is set, dwcmshc_cqhci_init() passes it to cqhci_set_cmd_idle_time() after cqhci_init(), and the CQHCI core programs it every time the CQE is enabled. Use it to set the CIT to 320 ns on StarFive JHB100 to improve eMMC CQE performance. Before/after dd results: before: dd if=/dev/mmcblk0 of=/dev/null bs=1M count=800 838860800 bytes (839 MB, 800 MiB) copied, 9.38511 s, 89.4 MB/s dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=800 838860800 bytes (839 MB, 800 MiB) copied, 12.2127 s, 68.7 MB/s after: dd if=/dev/mmcblk0 of=/dev/null bs=1M count=800 838860800 bytes (839 MB, 800 MiB) copied, 3.19472 s, 263 MB/s dd if=/dev/zero of=/dev/mmcblk0 bs=1M count=800 838860800 bytes (839 MB, 800 MiB) copied, 10.7587 s, 78.0 MB/s Signed-off-by: Changhuang Liang --- drivers/mmc/host/sdhci-of-dwcmshc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 249055f14162..afd392393ef5 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -283,6 +283,9 @@ #define PHY_DELAY_CODE_SD 0x55 #define PHY_DELAY_CODE_SDIO 0x29 +/* CIT for the JHB100 SoC */ +#define JHB100_CQHCI_CIT_NS 320 + struct rk35xx_priv { struct reset_control *reset; u8 txclk_tapnum; @@ -322,6 +325,7 @@ struct dwcmshc_priv { struct dwcmshc_pltfm_data { const struct sdhci_pltfm_data pdata; const struct cqhci_host_ops *cqhci_host_ops; + u32 cqhci_cit_ns; /* CQHCI Send Status Command Idle Timer */ int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); void (*deinit)(struct dwcmshc_priv *dwc_priv); void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); @@ -2412,6 +2416,7 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_jhb100_pdata = { .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, }, + .cqhci_cit_ns = JHB100_CQHCI_CIT_NS, .init = dwcmshc_starfive_jhb100_init, .deinit = dwcmshc_starfive_jhb100_deinit, }; @@ -2471,6 +2476,13 @@ static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device * goto int_clock_disable; } + if (pltfm_data->cqhci_cit_ns) { + err = cqhci_set_cmd_idle_time(cq_host, pltfm_data->cqhci_cit_ns); + if (err) + dev_warn(mmc_dev(host->mmc), + "Unable to set CQHCI command idle time: %d\n", err); + } + dev_dbg(mmc_dev(host->mmc), "CQE init done\n"); return; -- 2.25.1