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Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66C9.mail.protection.outlook.com (10.167.240.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.5 via Frontend Transport; Wed, 4 Nov 2026 12:50:14 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 714264091E31; Wed, 4 Nov 2026 20:44:12 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com Subject: [PATCH v5 0/5] dmaengine: arm-dma350: Add slave support and Sky1 integration Date: Wed, 4 Nov 2026 20:44:06 +0800 Message-ID: <20261104124411.296640-1-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66C9:EE_|TYZPR06MB6498:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 5c5bdb58-ece7-4638-6ee8-08df3a722c46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|23010399003|376014|1800799024|6133799003|10067099003|18002099003|3023799007|56012099006|261022075727099003|261026121527099003|261022105027099003|261028144727099003|261026140227099003|261021121427099003|261021123027099003|261009223027099003|261102123227099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DCHTL7T57ihp0TctpK3IRbfCOW0v0Dh2Ezcn+973+bBFXTuYpfr34caEo/Xt0pBWPJyRTxceRJJW+06GdNJE3uVujwY31p12a8cyViGZpse7AeYVnyckubZOzLv+fCZ43tHlNI0Z3el6T+aHNhlM29c7xWV2Fvt5G3JskDILV05rseDjIBu7y86lSsEsCCCCpmzlGP7NTnDm1cIb2CZ+rEPPNFCnjDPraPIoJBsHRapmC7zMysyg9U3gqxp1Ht24Byt20lmbsST9u5AwirC8XVQ/jn2egUDbK/8rIaDG8kvjnqZ0vzuKvaSHTI6nZD8RvZjlGk7NVbnilVtqqQCrSzHrAhID6sbEFtceWGA2XZjCa7sCKlxcwhhxgPIdXAL1wVIa46QUx8rLdVxdqx2dNIq1XCfK4CdUCRdWTHiYPpeZD7gnatBCaiPMdwMz65Sl X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 12:50:14.8547 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c5bdb58-ece7-4638-6ee8-08df3a722c46 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66C9.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6498 Hello, This series adds scatter-gather and cyclic slave transfer support to the Arm DMA-350 driver, then describes the clock, reset and DMA address view of the CIX Sky1 FCH integration. Patch 1 fixes the source-trigger bit. Patch 2 adds peripheral transfers with descriptor-owned resource mappings, coherent linked commands and hardware-based residue reporting. Patches 3 and 4 document and handle optional integration clocks and resets. Patch 5 describes the FCH DMA address windows and adds its bus clock. The controller nodes use arm,dma-350. The driver changes use standard integration resources and introduce no CIX-specific register programming. The companion AUDSS interrupt-path series builds on this one and manages the AUDSS interrupt gates in the CRU driver. Changes since v4: - Allow slave configuration updates while descriptors exist, and take a locked configuration snapshot when preparing transfers. (Sashiko.) - Derive cyclic residue from the hardware link pointer rather than a software period count. Retry changed samples and retain cached residue when a usable sample is not obtained. (Sashiko.) - Stop advertising undefined bus widths; validate trigger support and transfer widths per channel and report per-channel capabilities. (Sashiko.) - Remove the stopping flag and always poll STOPCMD during synchronization. Serialize IRQ status sampling, acknowledgement and descriptor selection under the channel lock. (Sashiko.) - After dmaengine_terminate_async(), the DMAengine API requires clients to call dmaengine_synchronize() before issuing new transfers. The start path continues to rely on that requirement. (Sashiko.) - Rebase onto Linux 7.4-rc1 and regenerate DTS context on the clean base. Keep patch 1 unchanged and retain Frank's Reviewed-by. Link: https://lore.kernel.org/r/20261023093017.3248454-1-Jelly.Jia@cixtech.com Signed-off-by: Jelly Jia Jelly Jia (5): dmaengine: arm-dma350: Fix source trigger bit dmaengine: arm-dma350: Add slave and cyclic transfer support dt-bindings: dma: arm,dma-350: Document optional clocks and resets dmaengine: arm-dma350: Support integration clocks and resets arm64: dts: cix: Describe the Sky1 FCH DMA-350 integration .../devicetree/bindings/dma/arm,dma-350.yaml | 16 +- arch/arm64/boot/dts/cix/sky1.dtsi | 36 +- drivers/dma/arm-dma350.c | 821 +++++++++++++++++- 3 files changed, 828 insertions(+), 45 deletions(-) base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.54.0