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Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E6.mail.protection.outlook.com (10.167.240.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.5 via Frontend Transport; Wed, 4 Nov 2026 12:50:20 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 872BF40920F7; Wed, 4 Nov 2026 20:44:38 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com, linux-clk@vger.kernel.org, joakim.zhang@cixtech.com Subject: [PATCH v2 1/5] dt-bindings: soc: cix: Describe the Sky1 AUDSS DMA IRQ controller Date: Wed, 4 Nov 2026 20:44:33 +0800 Message-ID: <20261104124437.296753-2-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261104124437.296753-1-Jelly.Jia@cixtech.com> References: <20261104124437.296753-1-Jelly.Jia@cixtech.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E6:EE_|TY1PPF4A2CDB296:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 7a7c5198-9c1d-42a4-4940-08df3a722f3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|1800799024|82310400026|36860700016|56012099006|261021121427099003|261021123027099003|261009223027099003|261026140227099003|261102123227099003|261022105027099003|261026121527099003|261028144727099003|10067099003|22082099003|18002099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lAqKGEuoRhhmSrBONapvi1VFQFUgRzokd8hCK6KL/mId09ojcqGmN9TbkHt+SCP0rfhMhVgxnUzK1M/ADXnLfswIbNcvw/yr+s/4b0Bf/wdBf9wqj0XnGMQlj5BMIb8LV1JyYikEg/wE1GEfMjb1Yqjr1A0L6fynYKDGGdWcN40+0tYTyWd3UCKR7gz2QB2FlUka7u7LJZ06kKXXm8O4FHrnsnBLQoJyS4syCH/61sqesNlSwhomJ6fIrwUMWt0siaonraTx5wMgttNUCeRlr9+lw0y5qEgveXb8d+EDdXSywPPhRwNkvC9I8JIsvD4R7zHAHq7hD8G5jqQDpD+2lE165ghW47/0HGQx/YJSKRYcD0qCaOFjEe2rrQSSHtKocKwe44XSVP/DA5pUn8v1agXokRcysQpcEva8ZNnTWDzCuTmzHRnjz+72CFcDZC6M X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 12:50:20.1380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a7c5198-9c1d-42a4-4940-08df3a722f3d X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E6.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY1PPF4A2CDB296 The AUDSS CRU contains a separate AP interrupt gate for each of the eight DMA-350 channels. The enabled inputs are combined onto one GIC interrupt. These gates are part of the CRU register block, not the DMA controller. Describe the CRU as an interrupt-controller in addition to its clock and reset functions. A child interrupt specifier contains the DMA channel index, matching the corresponding gate bit; the parent interrupt is the combined GIC line. Signed-off-by: Jelly Jia --- .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 37 ++++++++++++++++++- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml index 50dd0593e1d9..aa0c557abec0 100644 --- a/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml @@ -28,6 +28,12 @@ description: | The SoC syscon NoC (or bus) reset is described via resets. The audio subsystem power domain is described via power-domains. + The same register block contains the eight DMA-350 channel interrupt + gates at offset 0x54. When the node is an interrupt-controller, the + cell is the DMA channel index (0 through 7). The corresponding gate + bit is unmasked while that interrupt is requested, and the eight + inputs are combined onto the parent GIC interrupt. + properties: compatible: const: cix,sky1-audss-cru @@ -45,6 +51,18 @@ properties: description: Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: + The cell is the DMA-350 channel index, 0 through 7. + + interrupts: + maxItems: 1 + description: + Combined DMA-350 channel interrupt after the CRU gates. + clocks: items: - description: I2S parent clock for sampling rates multiple of 8kHz. @@ -75,18 +93,33 @@ required: - power-domains - resets +allOf: + - if: + required: + - interrupt-controller + then: + required: + - '#interrupt-cells' + - interrupts + additionalProperties: false examples: - | - audss_cru: clock-controller@7110000 { + #include + #include + + clock-controller@7110000 { compatible = "cix,sky1-audss-cru"; reg = <0x7110000 0x10000>; #clock-cells = <1>; - #reset-cells = <1>; clocks = <&scmi_clk 76>, <&scmi_clk 78>, <&scmi_clk 70>, <&scmi_clk 71>; clock-names = "x8k", "x11k", "sys", "48m"; + #interrupt-cells = <1>; + interrupt-controller; + interrupts = ; power-domains = <&smc_devpd 0>; + #reset-cells = <1>; resets = <&s5_syscon 31>; }; -- 2.54.0