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([39.170.101.209]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b09449bff2sm3920799a91.9.2026.11.04.04.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 04:50:37 -0800 (PST) From: Zxyan Zhu To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@kernel.org, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com Cc: mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, richardcochran@gmail.com, muhammad.nazim.amirul.nazle.asmade@altera.com, rohan.g.thomas@altera.com, o.rempel@pengutronix.de, wojciech.drewek@intel.com, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v9 0/3] net: stmmac: dwxgmac2: timestamp interrupt support + Agilex5 fix Date: Wed, 4 Nov 2026 20:50:27 +0800 Message-Id: <20261104125030.1183146-1-zxyan0222@gmail.com> X-Mailer: git-send-email 2.34.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds auxiliary snapshot (EXTTS) interrupt support to DWXGMAC2/DWXLGMAC2, fixes a stale TSIS race on the Agilex5 cross-timestamp path that the new handler would otherwise expose, and guards the shared aux snapshot handler against a zero channel mask. Patch 1 makes smtg_crosststamp() complete on the persistent ATSNS count instead of the transient TSIS bit, waits for the FIFO clear to complete, and holds aux_ts_lock across the whole trigger/poll/drain sequence so a concurrent EXTTS request cannot flush the snapshot FIFO mid-flight. Patch 2 guards the shared aux snapshot handler against a zero channel mask: ilog2() is applied to the mask without a zero check, and ilog2(0) yields an out-of-range event index that ptp_clock_event() feeds to test_bit() unchecked from hard IRQ context. Patch 3 adds a dedicated DWXGMAC2 timestamp interrupt handler. The XGMAC hwif entries used the generic ops, whose callback read the wrong register and whose enable mask omitted the timestamp interrupt, so the clock advertised the aux snapshot channels but no event was ever delivered. XGMAC_TSIE is not enabled by default; it is armed on demand from the EXTTS enable/disable path through a new callback, and the handler only touches the FIFO while the interrupt is armed and while no cross-timestamp owns it. The interrupt is disarmed on suspend and unregister and re-armed on resume. --- v1: https://lore.kernel.org/netdev/20260806-dwxgmac2-timestamp-irq-v1-1-c051c79c9d90@gmail.com/ v2: https://lore.kernel.org/netdev/20260810100221.9166-1-zxyan0222@gmail.com/ v3: https://lore.kernel.org/netdev/20260818132722.1852876-1-zxyan0222@gmail.com/ v4: https://lore.kernel.org/netdev/20260902131441.322167-1-zxyan0222@gmail.com/ v5: https://lore.kernel.org/netdev/20260910081020.86227-1-zxyan0222@gmail.com/ v6: https://lore.kernel.org/netdev/20260929073553.4136336-1-zxyan0222@gmail.com/ v7: https://lore.kernel.org/netdev/20261004120526.2728564-1-zxyan0222@gmail.com/ v8: https://lore.kernel.org/netdev/20261013033207.1684328-1-zxyan0222@gmail.com/ v9: - Check the already-enabled channel from the live PTP_ACR mask before programming it, so an enable for a channel other than the armed one is rejected with -EBUSY while a disable for a channel other than the armed one stays a no-op, and re-enabling the armed channel stays idempotent, disarming and draining the interrupt across the FIFO clear like a first enable. Requests are also refused while an internal cross-timestamp owns the FIFO. - Move the smtg_crosststamp() EXTTS check under aux_ts_lock so it cannot race a concurrent enable, and hold the lock across the SMTG register reads so a concurrent PTP_SYS_OFFSET_PRECISE cannot retrigger the snapshot while they run. - Hold aux_ts_lock across the whole of intel_crosststamp() as well, refuse to run once the clock has been invalidated by unregister, handle an interrupted wait, and disarm the internal snapshot trigger in both cross-timestamp paths on the way out, including the error paths. Drop the recorded EXTTS channel in the resume-failure teardown and at PTP clock unregister, on every core, disarming PTP_ACR or PTP_TCR as the core requires, so a leftover or re-armed trigger bit cannot reject later requests. -- 2.43.0