From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=185.67.36.66 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793806041; b=J2pcjTuU7yilxWiG8GvgR6F5Wr6ScQg/hS1l4LUScqeAiCT5OqcL0O2gus2rZ5+XWgCA 1ss3sFrqi6tdJBS/zAZe/xdXpAKNMit8I7PoyB07UizX/cax8CIzagKuciqMutqVjaYsy 13FutAzfd1mBqsjGD74g2LhxS89GgDy+TgFjusVYzWcFxwkD85J8a8O5DpvlqDho93/1N TXVVEOou2KoAgzeSMRiGJXRxTfEEdZNDbkOTri5vq25D8guxAe39UKLAcxU2V2b4eN3VG /QVzhjOpyV5RiTEh+Bw1XsFSsu3yDdnUcWrkYGavXB/6N6XFtTb5UZE19CkzDnTKvHg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793806041; h=DMARC-Filter:Received:DKIM-Signature:Received:From:To:Cc:Subject: Date:Message-ID:MIME-Version:Content-Transfer-Encoding; bh=iq05/Yj1rzuvCwAU0PCj1CRnJwTNnmq7BvvVMNO0EdU=; b=vhlrW9vlSw0zlz/JRmGKtsR+YVas9j8DQ4HqT+zXdtTJLuXDEoEUZQHcIO2ep4JrzicW PD+c6BXsvmchf1EJCPdfotOHgnUMf3LAsOKWNjWuoRIOCGmkKl/DCNJAaElN1/IsbWdbx ht1hoTP+aIBjdWLIOg0rBt+wrB/w6bkKmwuRJDWAuPAVymvOdBL/CE5FIorm8jaeEV+tm fvajhccWxvJ45u7BxN8feFzT5xa0CmfIW0NiqcdnNnwst/wFCFkuV/ScuFPPN2baRw43E zLH/JBUB3iKpG9QinNk/HhGAfJdKcWQ4gi4R9gzSk9v/lHDN5+zH0rg2Hir30LRBXnA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=posteo.net; spf=pass smtp.mailfrom=posteo.net; dkim=pass header.d=posteo.net header.i=@posteo.net header.a=rsa-sha256 header.s=1984.8680eb header.b=CBHyxZSC; arc=none smtp.remote-ip=185.67.36.66 Received: from mout02.posteo.de (mout02.posteo.de [185.67.36.66]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 566CA606A32C for ; Wed, 4 Nov 2026 15:27:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 566CA606A32C Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=posteo.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=posteo.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=posteo.net header.i=@posteo.net header.a=rsa-sha256 header.s=1984.8680eb header.b=CBHyxZSC Received: from submission (posteo.de [185.67.36.169]) by mout02.posteo.de (Postfix) with ESMTPS id 3A8E0240106 for ; Wed, 4 Nov 2026 16:27:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=posteo.net; s=1984.8680eb; t=1793806037; bh=iq05/Yj1rzuvCwAU0PCj1CRnJwTNnmq7BvvVMNO0EdU=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding:From; b=CBHyxZSCLmVhF+IEET0yBhJUYCg99wYQhD8qx1LZvJALwMUNYt6kC8+b3K74Q6eyH nsV4WM/QwUAygsa/AlNQZ6I+0kHmDyBum/6t/ScjaKfZytqJ6bpzB7u0V/U9TIa2br 22WIZlfPGmRBJ79eTeoCgkahkJmND2m7D+FtoWLtY32ktjELXcJX+w4hvoGgEMiOMu imc4hOUHQv+AiDLj2w3OZ7WQwD5ZiLaCdtnDJ800jgw6lFZseQCVhzn+efK9kTyvic TCA6XPSKpFjZUcCRwCXCxxoCPT+M/OUr27ffF8X/7y7p7YDZl9fYdLP/Mk2BbakogT rYcPfSh42D68g== Received: from customer (localhost [127.0.0.1]) by submission (posteo.de) with ESMTPSA id 4jKTnv22nLz9rxM; Wed, 4 Nov 2026 16:27:15 +0100 (CET) From: Mateusz Nowicki To: Ulf Hansson , linux-mmc@vger.kernel.org Cc: Mateusz Nowicki , Russell King , Linus Walleij , Yann Gautier , Christophe Kerello , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/5] mmc: mmci: stm32: silent data corruption and HS200 fixes Date: Wed, 04 Nov 2026 15:27:16 +0000 Message-ID: <20261104152657.14909-1-mateusz.nowicki@posteo.net> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The eMMC of the STM32MP257F-DK in HS200 returned stale data and lost writes without any error. Patch 1 makes data CRC errors visible to the core again. Patches 2 and 3 are the fixes of the ST downstream kernel for the causes seen on the DK, as Christophe pointed out. Patches 4 and 5 move the eMMC of the DK back to the sdmmc2 pins_a groups and remove the pins_b groups I added for it in 7.4: the corruption came from the delay block, not from the slew rate, and the slower pins avoid overshoots on the SDMMC2 clock. Patches 1-3 are for the mmc tree, 4 and 5 for the STM32 device tree, patch 4 needs patch 3. Tested on the STM32MP257F-DK with a v7.3-rc6 based kernel with the same changes, each run writing 832 MiB to the eMMC and reading it back: - SDMMC2 kernel clock 200 MHz, HS200 at 100 MHz as in mainline: without patch 3 the writes failed with I/O errors in all 9 runs (sdmmc2 pins_a or pins_b, with or without NEGEDGE), with it all 6 runs were correct (pins_a and pins_b). - SDMMC2 kernel clock 150 MHz, HS200 at 150 MHz with the delay block: all 6 runs correct (pins_a and pins_b), the tuning picked the same phase in all 10 rebinds on each pin group. Build tested on v7.4-rc1 (arm64 defconfig, W=1). Not tested on STM32MP1x. Changes in v2: - Drop "mmc: mmci: stm32: do not use NEGEDGE in HS200 mode". NEGEDGE has no effect with CLKDIV = 0 and is valid with a divider, I misread RM0457 (Christophe). The writes at 100 MHz fail because of the delay block, not NEGEDGE. - Replace "mmc: mmci: stm32: lock the STM32MP25 delay block again before tuning" with the same change from the ST downstream kernel, "mmc: mmci: stm32: release the delay block before enabling it" (Christophe). - Add "mmc: mmci: stm32: use the delay block above 100 MHz on stm32mp25 SoC" from the ST downstream kernel (Christophe), with dlyb checked before reading min_freq from it. - Add "arm64: dts: st: use sdmmc2 pins_a on stm32mp257f-dk" and "arm64: dts: st: remove sdmmc2 pins_b from stm32mp25" (Christophe). - Rebase on v7.4-rc1. - Link to v1: https://lore.kernel.org/r/20261031120700.42576-1-mateusz.nowicki@posteo.net Christophe Kerello (2): mmc: mmci: stm32: release the delay block before enabling it mmc: mmci: stm32: use the delay block above 100 MHz on stm32mp25 SoC Mateusz Nowicki (3): mmc: mmci: do not count a data CRC error as a complete transfer arm64: dts: st: use sdmmc2 pins_a on stm32mp257f-dk arm64: dts: st: remove sdmmc2 pins_b from stm32mp25 arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 58 ------------------- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 4 +- drivers/mmc/host/mmci.c | 5 +- drivers/mmc/host/mmci_stm32_sdmmc.c | 28 +++++++-- 4 files changed, 27 insertions(+), 68 deletions(-) base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.56.0