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Wed, 04 Nov 2026 07:59:34 -0800 (PST) Received: from Lord-Beerus.station ([93.66.71.207]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b2aae24b32sm140069925e9.12.2026.11.04.07.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 07:59:34 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org Cc: pierluigi.p@variscite.com, alexander.h@variscite.com, Stefano Radaelli , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Charles Keepax , Kuninori Morimoto , Linus Walleij , Kees Cook , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig=20=28The=20Capable=20Hub=29?= , patches@opensource.cirrus.com Subject: [PATCH v1 1/1] ASoC: wm8904: Enable FLL when switching an active SYSCLK to FLL Date: Wed, 4 Nov 2026 16:58:32 +0100 Message-ID: <20261104155832.57738-1-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli When switching SYSCLK from MCLK to FLL, DAPM may keep SYSCLK powered and skip the PRE_PMU event that normally enables the FLL. This leaves SYSCLK sourced from a disabled FLL and can cause playback to fail. Enable FLL_OSC_ENA and FLL_ENA before selecting FLL as the SYSCLK source when WM8904_CLK_SYS_ENA is already set. On VAR-SOM-MX8X, playing audio at 48 kHz followed immediately by 8 kHz reproduced an I/O error when switching from MCLK to FLL. With this change, playback succeeds. Co-developed-by: Alexander Herfurtner Signed-off-by: Alexander Herfurtner Signed-off-by: Stefano Radaelli --- sound/soc/codecs/wm8904.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index 96d2e54a2c6a..efa108544927 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -338,6 +338,20 @@ static int wm8904_configure_clocking(struct snd_soc_component *component) dev_dbg(component->dev, "Using %dHz FLL clock\n", wm8904->fll_fout); + /* The SYSCLK may already be on; if source changes to FLL, ensure + * FLL is enabled before selecting it as SYSCLK source. + */ + if (clock2 & WM8904_CLK_SYS_ENA) { + snd_soc_component_update_bits(component, + WM8904_FLL_CONTROL_1, + WM8904_FLL_OSC_ENA, + WM8904_FLL_OSC_ENA); + snd_soc_component_update_bits(component, + WM8904_FLL_CONTROL_1, + WM8904_FLL_ENA, + WM8904_FLL_ENA); + } + clock2 |= WM8904_SYSCLK_SRC; rate = wm8904->fll_fout; break; -- 2.47.3