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LL progress handling will use it to check for a stopped channel with no payload left to transfer. PCI Express DM Controller Databook 6.10a-lca06, section 7.3.4, "Detecting the End of the HDMA Transfer", documents this polling method: STATUS field of the HDMA Write/Read Channel Status register (HDMA_STATUS_OFF_[WR|RD]CH_i) is Stopped, and the HDMA Transfer Size register is 0x0. The same condition applies to eDMA as well. No functional change on its own. Cc: stable@vger.kernel.org Reviewed-by: Frank Li Signed-off-by: Koichiro Den --- Changes from v6: - Add Frank's Reviewed-by. - Add Cc:stable because patch 2 depends on this change. - No code changes. drivers/dma/dw-edma/dw-edma-core.h | 6 ++++++ drivers/dma/dw-edma/dw-edma-v0-core.c | 6 ++++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h index 76fd5a41a707..84a811bdcb6d 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -163,6 +163,7 @@ struct dw_edma_core_ops { int (*ch_quiesce)(struct dw_edma_chan *chan); u16 (*ch_count)(struct dw_edma *dw, enum dw_edma_dir dir); enum dma_status (*ch_status)(struct dw_edma_chan *chan); + u32 (*ch_transfer_size)(struct dw_edma_chan *chan); irqreturn_t (*handle_int)(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, dw_edma_handler_t handler); void (*non_ll_start)(struct dw_edma_chan *chan, struct dw_edma_burst *child); @@ -262,6 +263,11 @@ enum dma_status dw_edma_core_ch_status(struct dw_edma_chan *chan) return chan->dw->core->ch_status(chan); } +static inline u32 dw_edma_core_ch_transfer_size(struct dw_edma_chan *chan) +{ + return chan->dw->core->ch_transfer_size(chan); +} + static inline irqreturn_t dw_edma_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, dw_edma_handler_t handler) diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c index c053cb4c2844..fa8be85c7ac1 100644 --- a/drivers/dma/dw-edma/dw-edma-v0-core.c +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c @@ -318,6 +318,11 @@ static enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan) return DMA_ERROR; } +static u32 dw_edma_v0_core_ch_transfer_size(struct dw_edma_chan *chan) +{ + return GET_CH_32(chan->dw, chan->dir, chan->id, transfer_size); +} + static void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan) { struct dw_edma *dw = chan->dw; @@ -665,6 +670,7 @@ static const struct dw_edma_core_ops dw_edma_v0_core = { .ch_quiesce = dw_edma_v0_core_ch_quiesce, .ch_count = dw_edma_v0_core_ch_count, .ch_status = dw_edma_v0_core_ch_status, + .ch_transfer_size = dw_edma_v0_core_ch_transfer_size, .handle_int = dw_edma_v0_core_handle_int, .ll_data = dw_edma_v0_core_ll_data, .ll_link = dw_edma_v0_core_ll_link, diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index d42cb4ad49a2..aa430219d0af 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -156,6 +156,11 @@ static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan) return DMA_ERROR; } +static u32 dw_hdma_v0_core_ch_transfer_size(struct dw_edma_chan *chan) +{ + return GET_CH_32(chan->dw, chan->dir, chan->id, transfer_size); +} + static void dw_hdma_v0_core_clear_done_int(struct dw_edma_chan *chan) { struct dw_edma *dw = chan->dw; @@ -425,6 +430,7 @@ static const struct dw_edma_core_ops dw_hdma_v0_core = { .ch_quiesce = dw_hdma_v0_core_ch_quiesce, .ch_count = dw_hdma_v0_core_ch_count, .ch_status = dw_hdma_v0_core_ch_status, + .ch_transfer_size = dw_hdma_v0_core_ch_transfer_size, .handle_int = dw_hdma_v0_core_handle_int, .non_ll_start = dw_hdma_v0_core_non_ll_start, .ll_data = dw_hdma_v0_core_ll_data, -- 2.54.0