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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ed0919b739sm10610075ad.59.2026.11.04.09.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 09:59:39 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Anna Maniscalco , Rob Clark , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 3/6] drm/msm: Rework IFPC disable Date: Wed, 4 Nov 2026 09:59:23 -0800 Message-ID: <20261104175931.28475-4-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261104175931.28475-1-robin.clark@oss.qualcomm.com> References: <20261104175931.28475-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: -9hzQxsjUG6sciZhNOSn_dSClIN6Dlkz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA0MDA3MSBTYWx0ZWRfX7mL97r4u90OT UGqHyqjc3zCJ3kUwYNN7JUP1hxnX1iPIrt2+7bxDsh0AHzTnjEfAhkMuKDjAW64Y/C3iPKPv9LA P5kmg5RE4lhZoH5eBqAdEJHTuVMTP2JMR5Wj2ozX+tqbm/TYG6lIlWdtKOXbm2Q8ZrTpr+Dw6bo w43XmO8/LhynOOzKbCVg/FVQc9ClkWH8CJIfMDfrzDcoOP8fMgc7XCS0emMsBBQrXr13oUqs9TH ETpuNOVrcsHq5jA6uTjBJ1EtFKeP9ehmmisVLBXEEWS98KgODvfeSCU0VxbjMJp4MQfpuwzOk+f ho9HIkMKkPuQDNS7wgApW5sXY8ZqO0otTS2VfciDqWlt8bnLvbVDAnYFvO5wzafSc+LAOeZayJ1 aVsBnMU994VGyCcArgEhJXVJ6K7mmqoCaVlS8Mqzrn48pMzQa3PFFXKTuk7Xi2XKZJBw8VtXjGs MzDXt+grRQCmdTnbnIw== X-Proofpoint-GUID: -9hzQxsjUG6sciZhNOSn_dSClIN6Dlkz X-Authority-Analysis: v=2.4 cv=UuP2pOwB c=1 sm=1 tr=0 ts=6aeb728d cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=0FW7IQkLa0pm2cqxDqMA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA0MDA3MSBTYWx0ZWRfX6FCA6gZqAYw0 WadPW9ZI+E9xQzwvZ7xTXzNycs4J3ZkPCb3pigbEEZ0m6dGDuoxKj+/6gCINy5ONERIFcvAM/JQ qP6/LJqmpxTzXxCVdO3fRhIQWNlI8G4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-04_05,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 adultscore=0 spamscore=0 impostorscore=0 phishscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611040071 Previously this was coupled to SYSPROF level, which made sense at the time. But there are other places that we need to inhibit IFPC. So decouple it from the sysprof refcount. Now it has it's own refcount, so multiple threads can vote to inhibit IFPC safely. The renamed gpu->ifpc_update() simply applies the new state by setting or clearing an OOB request. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 28 +++++++++++---------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 5 ++--- drivers/gpu/drm/msm/msm_gpu.c | 1 + drivers/gpu/drm/msm/msm_gpu.h | 26 +++++++++++++++++++++---- drivers/gpu/drm/msm/msm_perfcntr.c | 6 ++---- drivers/gpu/drm/msm/msm_submitqueue.c | 16 +++++++++++---- 8 files changed, 56 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 662f09bec9d5..b02bcaa4bd96 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1443,7 +1443,7 @@ static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu) a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); } - if (test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + if (test_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); ret = a6xx_gmu_wait_for_idle(gmu); @@ -2128,31 +2128,25 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, return irq; } -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) +void a6xx_gmu_ifpc_update(struct msm_gpu *gpu) { - bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) || force_on; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; - /* Nothing to do if GPU is suspended. We will handle this during GMU resume */ - if (!pm_runtime_get_if_active(&gpu->pdev->dev)) - return; + /* Caller must hold a runpm ref: */ + drm_WARN_ON_ONCE(gpu->dev, pm_runtime_status_suspended(&gpu->pdev->dev)); + drm_WARN_ON_ONCE(gpu->dev, READ_ONCE(gpu->needs_hw_init)); - mutex_lock(&gmu->lock); + guard(mutex)(&gmu->lock); - /* - * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that, - * use the currently unused perfcounter oob vote to block IFPC when sysprof is active - */ - if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + bool ifpc_disable = refcount_read(&gpu->ifpc_disable) > 1; + + if (ifpc_disable && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) { a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) + } else if (!ifpc_disable && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) { a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - - mutex_unlock(&gmu->lock); - - pm_runtime_put(&gpu->pdev->dev); + } } void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 09d76cdf059f..2a4f81d14400 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1565,10 +1565,9 @@ static int hw_init(struct msm_gpu *gpu) a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); } - if (!ret && msm_gpu_sysprof_no_ifpc(gpu)) { + /* re-apply IFPC-disable OOB request, if needed: */ + if (!ret && test_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) { ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - if (!ret) - set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); } return ret; @@ -2851,7 +2850,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, @@ -2922,7 +2921,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a6xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, }, .init = a6xx_gpu_init, @@ -2953,7 +2952,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = { .create_private_vm = a6xx_create_private_vm, .get_rptr = a6xx_get_rptr, .progress = a8xx_progress, - .sysprof_setup = a6xx_gmu_sysprof_setup, + .ifpc_update = a6xx_gmu_ifpc_update, .perfcntr_configure = a6xx_perfcntr_configure, .perfcntr_flush = a8xx_perfcntr_flush, }, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 81d21acccea1..cdb830b7b778 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -298,7 +298,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); +void a6xx_gmu_ifpc_update(struct msm_gpu *gpu); void a6xx_preempt_init(struct msm_gpu *gpu); void a6xx_preempt_hw_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index e7d04c865968..ba8306e9eb44 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -846,10 +846,9 @@ static int hw_init(struct msm_gpu *gpu) */ a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); - if (!ret && msm_gpu_sysprof_no_perfcntr_zap(gpu)) { + /* re-apply IFPC-disable OOB request, if needed: */ + if (!ret && test_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status)) { ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); - if (!ret) - set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); } return ret; diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index ca21b3bf20df..07b7bd8d2329 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -1014,6 +1014,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, gpu->nr_rings = nr_rings; refcount_set(&gpu->sysprof_active, 1); + refcount_set(&gpu->ifpc_disable, 1); mutex_init(&gpu->perfcntr_lock); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index d27d54bdb7a7..0334a0f604ac 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -93,7 +93,7 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); - void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on); + void (*ifpc_update)(struct msm_gpu *gpu); /* Configure perfcntr SELect regs: */ void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring, @@ -186,6 +186,14 @@ struct msm_gpu { */ refcount_t sysprof_active; + /** + * ifpc_disable: + * + * Count of votes to disable IFPC (1-based, values above 1 mean IFPC + * is disabled). + */ + refcount_t ifpc_disable; + /** * lock: * @@ -375,10 +383,20 @@ msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) (gpu->perfcntrs && READ_ONCE(gpu->perfcntrs->stream)); } -static inline bool -msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) +static inline void +msm_gpu_disable_ifpc_get(struct msm_gpu *gpu) +{ + refcount_inc(&gpu->ifpc_disable); + if (gpu->funcs->ifpc_update) + gpu->funcs->ifpc_update(gpu); +} + +static inline void +msm_gpu_disable_ifpc_put(struct msm_gpu *gpu) { - return refcount_read(&gpu->sysprof_active) > 1; + refcount_dec(&gpu->ifpc_disable); + if (gpu->funcs->ifpc_update) + gpu->funcs->ifpc_update(gpu); } /* diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c index 36ce9a102c5e..8c2454627a8d 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -266,8 +266,7 @@ sample_worker(struct kthread_work *work) } /* Inhibit IFPC while accessing registers: */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, true); + msm_gpu_disable_ifpc_get(gpu); if (gpu->funcs->perfcntr_flush) gpu->funcs->perfcntr_flush(gpu); @@ -304,8 +303,7 @@ sample_worker(struct kthread_work *work) } /* Re-enable IFPC: */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, false); + msm_gpu_disable_ifpc_put(gpu); smp_store_release(&stream->fifo.head, head); wake_up_all(&stream->poll_wq); diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index e3e7c401fa5c..d41756c0152b 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -25,7 +25,13 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy pm_runtime_get(&gpu->pdev->dev); fallthrough; case 1: + /* Disable zapping perfcntrs on context switch: */ refcount_inc(&gpu->sysprof_active); + /* Disable IFPC: */ + scoped_guard (mutex, &gpu->lock) { + msm_gpu_hw_init(gpu); + msm_gpu_disable_ifpc_get(gpu); + } fallthrough; case 0: break; @@ -37,16 +43,18 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy pm_runtime_put_autosuspend(&gpu->pdev->dev); fallthrough; case 1: + /* Drop our vote for inhibiting IFPC: */ + scoped_guard (mutex, &gpu->lock) { + msm_gpu_hw_init(gpu); + msm_gpu_disable_ifpc_put(gpu); + } + /* Drop our vote for disabling perfcntr zapping: */ refcount_dec(&gpu->sysprof_active); fallthrough; case 0: break; } - /* Some gpu families require additional setup for sysprof */ - if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu, false); - ctx->sysprof = sysprof; return 0; -- 2.56.0