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Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH v4 7/9] x86/microcode: Use stop-machine NMI facility Date: Wed, 4 Nov 2026 18:23:20 +0000 Message-ID: <20261104182322.578066-8-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261104182322.578066-1-chang.seok.bae@intel.com> References: <20261104182322.578066-1-chang.seok.bae@intel.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The existing NMI-based loading logic explicitly sends NMIs to online CPUs and invokes microcode_update_handler() from the NMI context. The stop-machine NMI variant already provides the mechanism on x86. Replace the custom NMI control logic with stop_machine_nmi_cpuslocked(). Signed-off-by: Chang S. Bae --- arch/x86/Kconfig | 1 + arch/x86/include/asm/microcode.h | 1 - arch/x86/kernel/cpu/microcode/core.c | 19 +++---------------- arch/x86/kernel/nmi.c | 3 --- 4 files changed, 4 insertions(+), 20 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 58dce0b66179..f4bf1fdae6ba 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1325,6 +1325,7 @@ config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n depends on MICROCODE && SMP + select STOP_MACHINE_NMI help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequence diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 645e65ac1586..e6c09dc48efb 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -78,7 +78,6 @@ static inline u32 intel_get_microcode_revision(void) } #endif /* !CONFIG_CPU_SUP_INTEL */ -bool microcode_nmi_handler(void); void microcode_offline_nmi_handler(void); #ifdef CONFIG_MICROCODE_LATE_LOADING diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 9c006cc90047..73a46c6c74de 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -562,22 +562,9 @@ static noinstr int microcode_update_handler(void *unused) * path which must be NMI safe until the primary thread completed the * update. */ -bool noinstr microcode_nmi_handler(void) +static noinstr int microcode_nmi_handler(void *data) { - if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) - return false; - - raw_cpu_write(ucode_ctrl.nmi_enabled, false); - return microcode_update_handler(NULL) == 0; -} - -static int stop_cpu_in_nmi(void *unused) -{ - /* Enable the NMI handler and raise NMI */ - this_cpu_write(ucode_ctrl.nmi_enabled, true); - apic->send_IPI(smp_processor_id(), NMI_VECTOR); - - return 0; + return microcode_update_handler(data); } static int load_late_stop_cpus(bool is_safe) @@ -615,7 +602,7 @@ static int load_late_stop_cpus(bool is_safe) if (microcode_ops->use_nmi) { static_branch_enable_cpuslocked(µcode_nmi_handler_enable); - stop_machine_cpuslocked(stop_cpu_in_nmi, NULL, cpu_online_mask); + stop_machine_nmi_cpuslocked(microcode_nmi_handler, NULL, cpu_online_mask); static_branch_disable_cpuslocked(µcode_nmi_handler_enable); } else { stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index 0d426e5e74ee..e3660b8b8f38 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -391,9 +391,6 @@ static noinstr void default_do_nmi(struct pt_regs *regs) if (stop_machine_nmi_handler()) goto out; - if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) - goto out; - /* * CPU-specific NMI must be processed before non-CPU-specific * NMI, otherwise we may lose it, because the CPU-specific -- 2.53.0