[PATCH] clk: sunxi-ng: h6: Let the SPDIF clock set the audio PLL rate

[Jernej Skrabec <jernej.skrabec@gmail.com>]

Unlike the I2S clocks, the SPDIF clock can't change the audio PLL rate,
so it can only divide down the rate the PLL already runs at. That covers
only one of the 44.1 kHz and 48 kHz sample rate families, and the other
one is sent at the wrong rate.

Propagate rate changes to the parent, like the I2S clocks do.

Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 7fccda96d444..3e8e79871eb4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -571,7 +571,7 @@ static struct ccu_div spdif_clk = {
 		.hw.init	= CLK_HW_INIT_PARENTS("spdif",
 						      audio_parents,
 						      &ccu_div_ops,
-						      0),
+						      CLK_SET_RATE_PARENT),
 	},
 };
 

base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
-- 
2.43.0