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[46.122.103.30]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b56f02386bsm4031515e9.7.2026.11.04.10.51.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 10:51:51 -0800 (PST) From: Jernej Skrabec To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH] ARM: dts: sun8i: r40: bananapi-m2-ultra: Limit eMMC clock to 37.5 MHz Date: Wed, 4 Nov 2026 19:51:48 +0100 Message-ID: <20261104185148.883318-1-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Samsung eMMC on Banana Pi M2 Ultra fails with "data error, sending stop command" within a second of sustained reads in DDR52 mode at 50 MHz. At 37.5 MHz the same board survives a long read/write soak. Limit the eMMC clock to 37.5 MHz. Also enable the hardware reset line, which is routed to the controller (PC24), so the card can be recovered after such errors. Link: https://forum.libreelec.tv/thread/30663-banana-pi-m2u-emmc-data-error-sending-stop-command-fixed-with-a-40-mhz-device-tr/ Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts index cd2351acc32f..ddb70af25836 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts @@ -195,6 +195,8 @@ &mmc2 { vmmc-supply = <®_dcdc1>; vqmmc-supply = <®_dcdc1>; bus-width = <8>; + max-frequency = <37500000>; + cap-mmc-hw-reset; non-removable; status = "okay"; }; base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.43.0