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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36ca38d3754sm16263984eec.14.2026.11.04.20.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 20:01:14 -0800 (PST) Date: Wed, 4 Nov 2026 20:01:09 -0800 From: Jonathan Cameron To: "Santino Wang (=?utf-8?Q?=E7=8E=8B=E4=BF=8A=E5=82=91?=)" Cc: AngeloGioacchino Del Regno , "Fred-WY Chen (=?utf-8?Q?=E9=99=B3=E5=A8=81=E5=AE=87?=)" , "linux-kernel@vger.kernel.org" , "Light Chen (=?utf-8?Q?=E9=99=B3=E6=98=B1?= =?utf-8?Q?=E5=85=89?=)" , "linux-arm-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , "matthias.bgg@gmail.com" , Arnab Layek Subject: Re: [RFC PATCH 03/11] soc: mediatek: dram-ecc: add tracepoints Message-ID: <20261104200109.00002de4@oss.qualcomm.com> In-Reply-To: <3cc31b2f5cc226561c7c6642bcaeb85d3e22e9ff.camel@mediatek.com> References: <20261102092334.138759-1-santino.wang@mediatek.com> <20261102092334.138759-4-santino.wang@mediatek.com> <20261102115758.00005a16@oss.qualcomm.com> <3cc31b2f5cc226561c7c6642bcaeb85d3e22e9ff.camel@mediatek.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: uLOKOiV-KRsff3NNnMAChWUHuceKVJkw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDAxNSBTYWx0ZWRfX0joo6hsfeDRj HjOp4Y0TCxPDFLvw1DpNztGcnq1/Hl1J91gEX7baD+iwNtaHNYb0ZIt4jyvbUCozA6O52v8qtJK 3+jCuFi7B5FIiC/RS+zmA3xxAb4+9o9ybZ5EjkZnkMrZ/rrdSC/FCggVWLKgz4ytjtITzsiUv9L hqAKCMMZRNNZNdwOzENcp4WOdnfi3HyMsKLW8J3uQ/8loh3GZoTVnCFd+MBXgJVbRvZvdAKfn+3 gHZv6Bdo+VHC/9pVumBpb9Vr6rDkzaklYKdPwwckAbOZo4nomBCdPp9uG5QYXt2xOWZqvYuaRX5 Uk+a5TJRzo6JR33LvMZtxEwrUSJeu7UyrqCji00VuY3n/zROSpYKW/YKl1wYXhDZ5Zhz9kOVidD EOZsgebGahAiQkL9ruPdgTsrLfLRqI4kLQEslmx76Ww0lKQ/XWbSWYO9nCc2khYSSzvTDBOILAI VBF03c4WNKfHPVeO2CQ== X-Proofpoint-GUID: uLOKOiV-KRsff3NNnMAChWUHuceKVJkw X-Authority-Analysis: v=2.4 cv=SZdi5fRu c=1 sm=1 tr=0 ts=6aebff8c cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=NEAV23lmAAAA:8 a=mpaa-ttXAAAA:8 a=016yWS8getB5-smde8QA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDAxNSBTYWx0ZWRfX/tDva0Vw1dfa j59Oc178S7/CLqj9CdtItDZz5rkzZmsgDto7lA1bxpg5lZqYH6+IK4w9nTFoVQY3/0FgeZ1fNoW spB6O0P4kfvHN5Jgn8GiR22QuqQovf8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_01,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611050015 On Wed, 4 Nov 2026 02:44:05 +0000 Santino Wang (=E7=8E=8B=E4=BF=8A=E5=82=91) wrot= e: > Hi Jonathan, >=20 > I checked UEFI 2.11 Appendix N.2.5 and N.2.6. Both sections > define Node, Card, Module and Device fields, but I could not > find an explicit channel or subchannel field in Memory Error > Section 2. >=20 > On MT8992, these identify the DRAM channel and the subchannel > within that channel. Could you clarify which standard fields > or encoding should represent these two indices, particularly > the subchannel? Ah. You are indeed correct. My mistake! I confused things with the CXL spec equivalent which is fairly tightly bound to these entrees but apparently gained a channel and sub channel over them. It would be a straight forward addition. These days UEFI has a code first proposal path that would rapidly solve this gap. The process would start with a public discussion (this one fits that requirement) then a ticket filed on https://github.com/tianocore/edk2/issues?q=3Dis%3Aissue+state%3Aopen+label%= 3Atype%3Acode-first Any example of a related one is: https://github.com/tianocore/edk2/issues/13430 Alternatively you could encode it in the Device which would be a slight abuse of the current spec, so not sure I'd recommend doing that. Binding channel to this would be fine as a given device is only on one channel, but that is more of a stretch given subchannels in ddr5 and later. I'd strong favor not inventing a new error record unless you absolutely have to as that adds burden for all the userspace tooling etc. Jonathan >=20 > Thanks > Santino >=20 > On Mon, 2026-11-02 at 11:57 -0800, Jonathan Cameron wrote: > >=20 > > External email : Please do not click links or open attachments until > > you have verified the sender or the content. > >=20 > > =20 > > > diff --git a/drivers/soc/mediatek/dram-ecc/core/trace.c > > > b/drivers/soc/mediatek/dram-ecc/core/trace.c > > > new file mode 100644 > > > index 000000000000..9a8b20e48069 > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/dram-ecc/core/trace.c > > > @@ -0,0 +1,6 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +/* > > > + * Copyright (c) 2026 MediaTek Inc. > > > + */ > > > +#define CREATE_TRACE_POINTS > > > +#include "trace.h" > > > diff --git a/drivers/soc/mediatek/dram-ecc/core/trace.h > > > b/drivers/soc/mediatek/dram-ecc/core/trace.h > > > new file mode 100644 > > > index 000000000000..d603fc38f0a7 > > > --- /dev/null > > > +++ b/drivers/soc/mediatek/dram-ecc/core/trace.h > > > @@ -0,0 +1,119 @@ > > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > +/* > > > + * Copyright (c) 2026 MediaTek Inc. > > > + */ > > > +#undef TRACE_SYSTEM > > > +#define TRACE_SYSTEM mtk_dram_ecc > > > + > > > +#if !defined(_TRACE_MTK_DRAM_ECC_H) || > > > defined(TRACE_HEADER_MULTI_READ) > > > +#define _TRACE_MTK_DRAM_ECC_H > > > + > > > +#include > > > + > > > +/* driver lifecycle - state: 0=3Dinit, 1=3Dexit */ > > > + > > > +TRACE_EVENT(mtk_dram_ecc_lifecycle, > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_PROTO(int state), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_ARGS(state), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_STRUCT__entry( > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(int, state) > > > +=C2=A0=C2=A0=C2=A0=C2=A0 ), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_fast_assign( > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->state =3D state; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 ), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_printk("%s", __entry->state ? "driver re= moved" : "driver > > > initialized") > > > +); > > > + > > > +/* > > > + * ECC events - spa/channel/subchannel/rank/bank/row/column > > > decoded from the > > > + * ECCERR_INFO0/1 entry that determined severity (see > > > ghes_notifier.c), > > > + * mirroring ATF dram_ecc/mt8992/fiq.c's decode. No agent/master > > > ID: ATF's > > > + * GHES vendor section doesn't compute them (see > > > mtk_dram_ecc_event.h). > > > + */ > > > + > > > +TRACE_EVENT(mtk_dram_ecc_ce, =20 > >=20 > > Why push these through a custom tracepoint?=C2=A0 This look very similar > > to what > > is in the Memory Error Section 2 CPER. > > =20 > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_PROTO(u64 spa, u8 channel, u8 subch, u16= rank, u16 bank, > > > u32 row, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 u16 column), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_ARGS(spa, channel, subch, rank, bank, ro= w, column), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_STRUCT__entry( > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u64, spa) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u8, channel) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u8, subch) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u16, rank) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u16, bank) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u32, row) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u16, column) > > > +=C2=A0=C2=A0=C2=A0=C2=A0 ), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_fast_assign( > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->spa=C2=A0=C2=A0=C2=A0=C2=A0 =3D spa; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->channel =3D channel; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->subch=C2=A0=C2=A0 =3D subch; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->rank=C2=A0=C2=A0=C2=A0 =3D rank; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->bank=C2=A0=C2=A0=C2=A0 =3D bank; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->row=C2=A0=C2=A0=C2=A0=C2=A0 =3D row; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->column=C2=A0 =3D column; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 ), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_printk("spa=3D0x%016llx ch=3D%u subch=3D= %u rank=3D%u bank=3D%u > > > row=3D%u column=3D%u", > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 __entry->spa, __entry->channel, __entry->subch, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 __entry->rank, __entry->bank, __entry->row, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 __entry->column) > > > +); > > > + > > > +TRACE_EVENT(mtk_dram_ecc_uce, > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_PROTO(u64 spa, u8 channel, u8 subch, u16= rank, u16 bank, > > > u32 row, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 u16 column), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_ARGS(spa, channel, subch, rank, bank, ro= w, column), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_STRUCT__entry( > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u64, spa) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u8, channel) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u8, subch) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u16, rank) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u16, bank) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u32, row) > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __field(u16, column) > > > +=C2=A0=C2=A0=C2=A0=C2=A0 ), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_fast_assign( > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->spa=C2=A0=C2=A0=C2=A0=C2=A0 =3D spa; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->channel =3D channel; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->subch=C2=A0=C2=A0 =3D subch; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->rank=C2=A0=C2=A0=C2=A0 =3D rank; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->bank=C2=A0=C2=A0=C2=A0 =3D bank; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->row=C2=A0=C2=A0=C2=A0=C2=A0 =3D row; > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 __entry->column=C2=A0 =3D column; > > > +=C2=A0=C2=A0=C2=A0=C2=A0 ), > > > +=C2=A0=C2=A0=C2=A0=C2=A0 TP_printk("spa=3D0x%016llx ch=3D%u subch=3D= %u rank=3D%u bank=3D%u > > > row=3D%u column=3D%u", > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 __entry->spa, __entry->channel, __entry->subch, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 __entry->rank, __entry->bank, __entry->row, > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 __entry->column) > > > +); =20 > > =20 >=20