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[2.155.41.158]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b56f5e65b0sm15526735e9.11.2026.11.04.13.58.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 13:58:52 -0800 (PST) From: =?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= To: shawn.lin@rock-chips.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, dlemoal@kernel.org, iav@iav.lv, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Enrique=20Hern=C3=A1ndez=20Bello?= Subject: [PATCH v5 1/2] dt-bindings: PCI: rockchip,rk3399-pcie: Add PERST# inactive delay properties Date: Wed, 4 Nov 2026 21:58:46 +0000 Message-ID: <20261104215848.2087944-2-ehbello@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261104215848.2087944-1-ehbello@gmail.com> References: <20261104215848.2087944-1-ehbello@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver holds PERST# asserted for T_PVPERL (100 ms) before releasing it. Endpoints disagree about what they want there: some need longer than the default to settle, while others stop answering configuration reads when the reset pulse is stretched that far, because PERST# stays asserted for the whole wait. Describe two properties so a board can state what its endpoint needs, named after the ones the Rockchip vendor driver already uses for the dwc-based controllers: rockchip,perst-inactive-ms - the delay used at probe rockchip,s2r-perst-inactive-ms - the delay used when resuming Both are optional and the defaults preserve the current behaviour. Signed-off-by: Enrique Hernández Bello --- .../bindings/pci/rockchip,rk3399-pcie.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml index 720a5f9..7ac915c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml @@ -40,6 +40,21 @@ properties: maxItems: 1 description: pre-reset GPIO + rockchip,perst-inactive-ms: + default: 100 + description: + Time PERST# is held asserted before it is released, which is also the + width of the reset pulse. The default meets T_PVPERL for a slot that + is powered at the moment PERST# is asserted. Some endpoints need more + settling time than that, while others stop responding when the pulse + is that long. A value of 0 selects the 100 us minimum the PCI Express + CEM specification sets for the pulse. + + rockchip,s2r-perst-inactive-ms: + description: + The same time, applied when resuming from system suspend. Defaults to + the value of rockchip,perst-inactive-ms. + vpcie12v-supply: description: The 12v regulator to use for PCIe. -- 2.56.0