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Wed, 04 Nov 2026 14:00:05 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ed08fe1e4dsm11237865ad.21.2026.11.04.14.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 14:00:04 -0800 (PST) From: Rosen Penev To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Bartosz Golaszewski , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/5] gpio: ppc44x: factor out the OSR/TSR source selection Date: Wed, 4 Nov 2026 13:59:56 -0800 Message-ID: <20261104215959.24035-3-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261104215959.24035-1-rosenp@gmail.com> References: <20261104215959.24035-1-rosenp@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Both direction callbacks clear the pin's 2-bit field in the output source and three-state source registers, picking the low or high register by bank. Move that into a helper instead of duplicating the if/else in each callback. No functional change; the registers are written in the same order. Signed-off-by: Rosen Penev --- drivers/gpio/gpio-ppc44x.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/gpio-ppc44x.c b/drivers/gpio/gpio-ppc44x.c index 01dd5e7cc311..b3cbc832cf24 100644 --- a/drivers/gpio/gpio-ppc44x.c +++ b/drivers/gpio/gpio-ppc44x.c @@ -64,6 +64,21 @@ static inline void ppc44x_setbits32(void __iomem *addr, u32 mask) iowrite32be(val, addr); } +/* + * Route the pin's output and three-state control to the GPIO controller + * rather than an alternate function. Bits 0-15 use OSRL/TSRL, bits 16-31 + * use OSRH/TSRH. + */ +static void ppc44x_gpio_select_gpio(struct ppc44x_gpio __iomem *regs, + unsigned int gpio) +{ + __be32 __iomem *osr = gpio < 16 ? ®s->osrl : ®s->osrh; + __be32 __iomem *tsr = gpio < 16 ? ®s->tsrl : ®s->tsrh; + + ppc44x_clrbits32(osr, GPIO_MASK2(gpio)); + ppc44x_clrbits32(tsr, GPIO_MASK2(gpio)); +} + /* * GPIO LIB API implementation for GPIOs * @@ -99,14 +114,7 @@ static int ppc44x_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) ppc44x_clrbits32(®s->tcr, GPIO_MASK(gpio)); gen_gc->sdir &= ~GPIO_MASK(gpio); - /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */ - if (gpio < 16) { - ppc44x_clrbits32(®s->osrl, GPIO_MASK2(gpio)); - ppc44x_clrbits32(®s->tsrl, GPIO_MASK2(gpio)); - } else { - ppc44x_clrbits32(®s->osrh, GPIO_MASK2(gpio)); - ppc44x_clrbits32(®s->tsrh, GPIO_MASK2(gpio)); - } + ppc44x_gpio_select_gpio(regs, gpio); return 0; } @@ -130,14 +138,7 @@ ppc44x_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) ppc44x_setbits32(®s->tcr, GPIO_MASK(gpio)); gen_gc->sdir |= GPIO_MASK(gpio); - /* Bits 0-15 use TSRL, bits 16-31 use TSRH */ - if (gpio < 16) { - ppc44x_clrbits32(®s->osrl, GPIO_MASK2(gpio)); - ppc44x_clrbits32(®s->tsrl, GPIO_MASK2(gpio)); - } else { - ppc44x_clrbits32(®s->osrh, GPIO_MASK2(gpio)); - ppc44x_clrbits32(®s->tsrh, GPIO_MASK2(gpio)); - } + ppc44x_gpio_select_gpio(regs, gpio); pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val); -- 2.56.0