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([220.120.90.131]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ed0908587dsm10999175ad.36.2026.11.04.15.02.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 15:02:53 -0800 (PST) From: Anisa Su X-Google-Original-From: Anisa Su To: linux-cxl@vger.kernel.org Cc: nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org, Dave Jiang , Alison Schofield , Jonathan Cameron , Davidlohr Bueso , Ira Weiny , Vishal Verma , Fan Ni , Li Ming , Benjamin Cheatham , Gregory Price , Richard Cheng , Anisa Su Subject: [PATCH v1 07/14] cxl/mem: Drop misaligned DCD extent groups Date: Thu, 5 Nov 2026 08:02:31 +0900 Message-ID: <20261104230445.66625-8-anisa.su@samsung.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261104230445.66625-1-anisa.su@samsung.com> References: <20261104230445.66625-1-anisa.su@samsung.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Ira Weiny Add an alignment gate, cxl_validate_group(), that cxl_add_pending() runs before realizing a tag group: every extent in the group must have its start_dpa and length aligned to the dax region's mapping granularity. A misaligned extent makes the resulting dax device unusable, so drop the whole group rather than accept a partial allocation that would surface a broken dax_resource. Based on patches by John Groves. Signed-off-by: Ira Weiny Co-developed-by: John Groves Signed-off-by: John Groves Co-developed-by: Anisa Su Signed-off-by: Anisa Su Tested-by: Wonjae Lee Tested-by: Junhee Park Tested-by: Heesoo Kim --- drivers/cxl/core/mbox.c | 46 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 18044f216de5..a605ffc4c64f 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include #include @@ -1395,6 +1397,19 @@ static int stage_pending_extent(struct list_head *pending, return 0; } +/* + * Extents need to be aligned to dax region's mapping granularity. + * Use PMD_SIZE, since cxl_dax_region_probe() calls alloc_dax_region with + * PMD_SIZE for the 'align' parameter. + */ +static bool cxl_extent_dcd_aligned(const struct cxl_extent *extent) +{ + u64 start = le64_to_cpu(extent->start_dpa); + u64 len = le64_to_cpu(extent->length); + + return IS_ALIGNED(start, PMD_SIZE) && IS_ALIGNED(len, PMD_SIZE); +} + /* * Compare two extents by shared_extn_seq (ascending). list_sort is * stable, so extents with equal keys keep their arrival order from @@ -1497,6 +1512,32 @@ static int cxl_realize_group(struct cxl_memdev_state *mds, const uuid_t *tag, return rc; } +/* + * Validate a tag @group before realizing it. Returns 0 if the group may be + * added, or a negative errno if it must be dropped. + */ +static int cxl_validate_group(struct cxl_memdev_state *mds, const uuid_t *tag, + struct list_head *group) +{ + struct device *dev = mds->cxlds.dev; + struct cxl_extent_list_node *pos; + + /* Alignment gate — drop the group if any member fails */ + list_for_each_entry(pos, group, list) { + if (!cxl_extent_dcd_aligned(pos->extent)) { + dev_warn_ratelimited(dev, + "Tag %pUb: dropping group, extent DPA:%#llx LEN:%#llx not %#llx-aligned\n", + tag, + le64_to_cpu(pos->extent->start_dpa), + le64_to_cpu(pos->extent->length), + (u64)PMD_SIZE); + return -EINVAL; + } + } + + return 0; +} + /* * Drive the pending Add-Capacity records through cxl_realize_group() one * tag group at a time, moving each group that realizes onto the accepted @@ -1541,6 +1582,11 @@ static int cxl_add_pending(struct cxl_memdev_state *mds, */ list_sort(NULL, &group, extent_seq_compare); + if (cxl_validate_group(mds, &tag, &group)) { + drop_extent_group(&group); + continue; + } + cnt = cxl_realize_group(mds, &tag, &group); if (cnt < 0) { drop_extent_group(&group); -- 2.43.0