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Thu, 5 Nov 2026 06:36:30 -0500 (EST) From: Janne Grunau Date: Thu, 05 Nov 2026 12:36:01 +0100 Subject: [PATCH 4/7] arm64: dts: apple: t6031: Add PCIe nodes X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261105-apple-m3-pcie-v1-4-e00a72a604f8@jannau.net> References: <20261105-apple-m3-pcie-v1-0-e00a72a604f8@jannau.net> In-Reply-To: <20261105-apple-m3-pcie-v1-0-e00a72a604f8@jannau.net> To: Sven Peter , Neal Gompa , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mark Kettenis , Joshua Peisach , Michael Reeves Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Janne Grunau , Yureka Lilian X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6804; i=j@jannau.net; h=from:subject:message-id; bh=x77/1VYiLOv5Z/RiZPfZfLJlhGGqM59JzKpcO+5IWaw=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhqw3WRql19y87+SrdLPteN29cU5/wjXJiVsmM8v9KzwZk G1UeL+qYyILgxgXg6WYIkuS9ssOhtU1ijG1D8Jg5rAygQyRFmlgAAIWBr7cxLxSIx0jPVNtQz1D Ix1jHSMGLk4BmOrrSxgZXv051ZX4cut8w22Wpoy+QTp/tHXrZRWVi6977CzpncvfxfBXIK7mDPM +/RVMGyNnif5mmTZ/T1/pxXlGH7etPnR3TutvVgA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 From: Yureka Lilian Add the PCIe controller, its ports, IOMMUs and clock request pins to the die0 M3 Max/Ultra .dtsi file. All M3 Max and Ultra devices use port 0 and 1 so enable them and their IOMMU. Signed-off-by: Yureka Lilian Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/t6031-die0.dtsi | 157 +++++++++++++++++++++++++ arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi | 9 ++ arch/arm64/boot/dts/apple/t6031.dtsi | 1 + 3 files changed, 167 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6031-die0.dtsi b/arch/arm64/boot/dts/apple/t6031-die0.dtsi index b14443436e26..434b16b2a6bf 100644 --- a/arch/arm64/boot/dts/apple/t6031-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t6031-die0.dtsi @@ -207,4 +207,161 @@ serial0: serial@391200000 { status = "disabled"; }; + + pcie0: pcie@580000000 { + device_type = "pci"; + compatible = "apple,t6031-pcie", "apple,t6020-pcie"; + + reg = <0x5 0x80000000 0x0 0x1000000>, /* config */ + <0x5 0x91000000 0x0 0x4000>, /* rc */ + <0x5 0x94008000 0x0 0x4000>, /* port0 */ + <0x5 0x95008000 0x0 0x4000>, /* port1 */ + <0x5 0x96008000 0x0 0x4000>, /* port2 */ + <0x5 0x97008000 0x0 0x4000>, /* port3 */ + <0x5 0x9e020000 0x0 0x4000>, /* phy0 */ + <0x5 0x9e024000 0x0 0x4000>, /* phy1 */ + <0x5 0x9e028000 0x0 0x4000>, /* phy2 */ + <0x5 0x9e02c000 0x0 0x4000>; /* phy3 */ + reg-names = "config", "rc", + "port0", "port1", "port2", "port3", + "phy0", "phy1", "phy2", "phy3"; + + ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; + #address-cells = <3>; + bus-range = <0 4>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_1 1 1>, + <0x300 &pcie0_dart_2 1 1>, + <0x400 &pcie0_dart_3 1 1>; + iommu-map-mask = <0xff00>; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 0 1854 IRQ_TYPE_EDGE_RISING 32>; + + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + power-domains = <&ps_apcie_sys_gp>; + #size-cells = <2>; + + port00: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + #address-cells = <3>; + + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + interrupt-map-mask = <0 0 0 7>; + reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>; + #size-cells = <2>; + }; + + port01: pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + ranges; + #address-cells = <3>; + + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map = <0 0 0 1 &port01 0 0 0 0>, + <0 0 0 2 &port01 0 0 0 1>, + <0 0 0 3 &port01 0 0 0 2>, + <0 0 0 4 &port01 0 0 0 3>; + interrupt-map-mask = <0 0 0 7>; + reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>; + #size-cells = <2>; + }; + + port02: pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + ranges; + #address-cells = <3>; + + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + interrupt-map-mask = <0 0 0 7>; + reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>; + #size-cells = <2>; + + status = "disabled"; + }; + + port03: pci@3,0 { + device_type = "pci"; + reg = <0x1800 0x0 0x0 0x0 0x0>; + ranges; + #address-cells = <3>; + + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map = <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + interrupt-map-mask = <0 0 0 7>; + reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>; + #size-cells = <2>; + + status = "disabled"; + }; + }; + + pcie0_dart_0: iommu@594000000 { + compatible = "apple,t6031-dart", "apple,t8110-dart"; + reg = <0x5 0x94000000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_apcie_sys_gp>; + }; + + pcie0_dart_1: iommu@595000000 { + compatible = "apple,t6031-dart", "apple,t8110-dart"; + reg = <0x5 0x95000000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_apcie_sys_gp>; + }; + + pcie0_dart_2: iommu@596000000 { + compatible = "apple,t6031-dart", "apple,t8110-dart"; + reg = <0x5 0x96000000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_apcie_sys_gp>; + + status = "disabled"; + }; + + pcie0_dart_3: iommu@597000000 { + compatible = "apple,t6031-dart", "apple,t8110-dart"; + reg = <0x5 0x97000000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_apcie_sys_gp>; + + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi index 0c0d09964e69..1c29d0ef8a67 100644 --- a/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi +++ b/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi @@ -5,6 +5,8 @@ * Copyright The Asahi Linux Contributors */ +#include + &pinctrl_ap { i2c0_pins: i2c0-pins { pinmux = , @@ -50,4 +52,11 @@ i2c8_pins: i2c8-pins { pinmux = , ; }; + + pcie_pins: pcie-pins { + pinmux = , + , + , + ; + }; }; diff --git a/arch/arm64/boot/dts/apple/t6031.dtsi b/arch/arm64/boot/dts/apple/t6031.dtsi index 30a91c1a47d2..9fd1d0f46fc3 100644 --- a/arch/arm64/boot/dts/apple/t6031.dtsi +++ b/arch/arm64/boot/dts/apple/t6031.dtsi @@ -5,6 +5,7 @@ * Copyright The Asahi Linux Contributors */ +#include #include #include #include -- 2.56.0