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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-945d488f183sm438320685a.39.2026.11.05.03.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 03:11:19 -0800 (PST) From: Wenmeng Liu Subject: [PATCH RFC 0/3] Support the Nord CCI CCU output mux Date: Thu, 05 Nov 2026 19:10:58 +0800 Message-Id: <20261105-ccu-v1-0-3accc4b901de@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAENk7GoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzNDQwNT3eTkUl1LS3ML00RTs5TkFAMloMqCotS0zAqwKdFKQW7OSrEQwaL UwlKgiSUQmdjaWgDg2c71bwAAAA== X-Change-ID: 20261105-ccu-99785a56dcd0 To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti Cc: mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, vikram.sharma@oss.qualcomm.com, nihal.gupta@oss.qualcomm.com, vtumati@quicinc.com, bryan.odonoghue@linaro.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793877074; l=2583; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=46oTe7kPy7FuqPo9XNr2S/V6jdi+yv6WkUX1TjqwpPM=; b=Dol529a6/PFWr/JmX2UCTfZDRm+kygGEkLiJ5I4XGx49aXLdT+Sl4/aG0KJUZRGVrOtpfvGyd 4gV/RXtflxMBM/DfYF5SIV5V1/JEo4mgZ8kk/3WcZgDOVFHp2oa75LU X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDA0NCBTYWx0ZWRfX4Ecz5U5EZPo6 BRmYqfLwyaI9bAid4H9l6bCMLkdbGRqdtkrYmDfVPLNR4IfwmZ9dkkdzP2+MJa1MKmp1h/+WsAv 5+WqMOkS0RPJom0feOUy5LTNHJK9XhI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDA0NCBTYWx0ZWRfX7Lt87ecU2YzQ LcGI0+dpjghJmqNcZk5fThCCLyVNwdstTao0Uh9bCVwuOCWPD+7jnN+jFp1zpqE4jGmuEoQAEbI UcDD44Lp5hCiAw42BmxZa1SbCa8n0RzAKTg7oJcTmdgwjii28/sXtqGVcYbraboHv9G1zQvFxqB zdWETCJdZHu8XQMRs3rnnAMLE4UD2zypa+XBMvdy5zrTS68yy145rf9aVJK4RUZALblWZcMOiDO Yo0a0nlAoG+3GYzJHDhl5u+lU7XimGdYOzcqOK3T9S54l3N1vbrznYnInwv+GfLNXGu7j5+OZ2g MZCfwNNWueib8mmoj+BOWvNeKNnOTgXr7ssafvX6xvMlQPk8G1BKd2IKpHevfkij7iloKS+Z5We 7/P0CoXZzbeY8nGmxydMlzvpvqISG8uWbTr1C/6ejc+IL+KeA8yfgcHYdujMheKIjDyqORgOe6q 7TV8gWeBEOA35KIw3gA== X-Proofpoint-ORIG-GUID: k2-zXf8POh7ksWsRYZyifOSNQ94iL-9S X-Proofpoint-GUID: k2-zXf8POh7ksWsRYZyifOSNQ94iL-9S X-Authority-Analysis: v=2.4 cv=Y5JtIReN c=1 sm=1 tr=0 ts=6aec645a cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=zavQIZ2TttM9Dy2BN-UA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_03,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611050044 On Nord, the CCI controllers are wrapped by a CCU. After reset, the CCI I2C ports are routed to the CCU, and the CCU output mux must select the CCI before it can be used. The mux register is part of CAM_TOP, a register block shared by multiple camera components and outside the CCI and CAMSS register ranges. Accessing the block requires the camera subsystem top power domain and AHB clock, and its state is lost when the power domain is turned off. This RFC describes CAM_TOP as a syscon and lets each CCI reference its mux configuration through a phandle, register offset and mask. The CCI driver selects the CCI at probe and runtime resume, right after enabling the CCI clocks and before the CCI is reset or configured. titan_cam_top: syscon@ { compatible = "qcom,nord-titan-cam-top", "syscon"; reg = <...>; }; cci2: cci@ { compatible = "qcom,nord-cci", "qcom,msm8996-cci"; ... qcom,ccu-mux-sel = <&titan_cam_top OFFSET MASK>; }; The CAM_TOP syscon does not describe its clock or power domain. A clock attached to a syscon is kept prepared for the lifetime of the regmap, which would keep the camera clock controller runtime active even when the camera is idle. Instead, the CCI, as the consumer, writes the mux with its own power domain and clocks, which include the AHB clock, enabled. An alternative is to introduce a dedicated CAM_TOP driver which owns the clock and power domain, provides the regmap through of_syscon_register_regmap() and handles runtime PM in its accessors. This describes the hardware resources more completely and avoids the debugfs issue, but adds a driver for a block currently used only by the CCI. We would like feedback on whether using a plain syscon with power and clock management left to its consumer is acceptable, or whether CAM_TOP should instead have a dedicated binding and driver. --- Wenmeng Liu (3): dt-bindings: mfd: syscon: Add Qualcomm Nord Titan CAM_TOP dt-bindings: i2c: qcom-cci: Document Nord compatible i2c: qcom-cci: Support the CCU output mux .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 41 +++++++++++++++++++++ Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-qcom-cci.c | 42 ++++++++++++++++++++++ 4 files changed, 85 insertions(+) --- base-commit: 8b7179210b22f8e48a82c5ceacb9d56a9c4cfec4 change-id: 20261105-ccu-99785a56dcd0 Best regards, -- Wenmeng Liu