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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-945d488f183sm438320685a.39.2026.11.05.03.11.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 03:11:45 -0800 (PST) From: Wenmeng Liu Date: Thu, 05 Nov 2026 19:11:01 +0800 Subject: [PATCH RFC 3/3] i2c: qcom-cci: Support the CCU output mux X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261105-ccu-v1-3-3accc4b901de@oss.qualcomm.com> References: <20261105-ccu-v1-0-3accc4b901de@oss.qualcomm.com> In-Reply-To: <20261105-ccu-v1-0-3accc4b901de@oss.qualcomm.com> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti Cc: mfd@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, vikram.sharma@oss.qualcomm.com, nihal.gupta@oss.qualcomm.com, vtumati@quicinc.com, bryan.odonoghue@linaro.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793877074; l=4082; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=0Fgpwz3SQDHyUhRlUEIFbbEDDaZfQdLbmmNOfyqJ+NI=; b=YEvUVTUPuMY1/we+4fCKvKq9lfIf2BdKLFRArkIbb6oKdgc5OVq5MkqizBFK1UnH3T87uagqR JQw75XFP5BED152z8NXXnVxhKstgxmfbx2tdKQFMaeDvyOcEgz2SRx2 X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-ORIG-GUID: r-aWv8yvbxK1UqDIQuBGQLTK1BeX1Rjm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDA0NCBTYWx0ZWRfX8WYZm3dhS8sR Dz/G1Bn35Pgoz9wscWPfKuPY3N6ap0mS0otCOvvZk2IZ5YFdExXR6vD++5do+ONujZu09aXllsU +cNY9HNTO20aexZL3dVr2kl33W0Gekjom9eS+R3rvG62aq3QzbDaTfV5uTAjzPGbdcDrUHoJVRD ie8c4j6maYkwpu6lb8mKIh+3Fb82o26H0EZKTrmMvPHT/y2AQ/LUqhNYO78AuWvLMo1HXs8eGSp 2Hk/XapHu860vBhT8bc/p4O+Wbwo7xhP4Itfu3B5Vq/oI+ptu+G3WW5aIp7pGRit4350PCjGvAB NNemTDCv84IJp9K9V59lPENoQHx2sHY6ThTryngZjqHKXH6k+I5x5mNFNZh/LvO6SFYuZLZQKW1 Pq0dek3WraGCVpZuuOr0szJXW5lQLbP0XPaBEBPcBEqja/hbsq1Y7wgLj0MCLfoTX3XgS9Exzaj GTB9693WV9vJmZgRnBQ== X-Proofpoint-GUID: r-aWv8yvbxK1UqDIQuBGQLTK1BeX1Rjm X-Authority-Analysis: v=2.4 cv=SZdi5fRu c=1 sm=1 tr=0 ts=6aec6473 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=mtkgQ_vjiMZ5qraaaqMA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDA0NCBTYWx0ZWRfXy8aEgr2bOXr2 jFC1BLi7E+byEX6ZzGNOQ2r+tA0s7i/NJEhWeN0u5qOJ1fNx87vmlZ1AQ5kwaxhFBBvbylZqdfd 1XUAdNGa2QFT7H8oWqWfe/FCjgd+kEQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_03,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 spamscore=0 adultscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611050044 On SoCs such as Nord, the CCIs are wrapped by a CCU. After reset, the CCI I2C ports are routed to the CCU, and the CCU output mux must select the CCI before any transfer can take place. Get the mux register and bits from the optional qcom,ccu-mux-sel syscon reference and select the CCI at probe and runtime resume, right after enabling the CCI clocks and before the CCI is reset or configured, as the mux register is not retained across power collapse. The mux register is accessible only with the camera subsystem top power domain and AHB clock enabled, both of which are CCI resources. The syscon regmap serializes the accesses from multiple CCI instances. Signed-off-by: Wenmeng Liu --- drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-qcom-cci.c | 42 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 275aaa7f35833f0b07ae13e88def21c3fbc6c787..63ba7314ee7c7cc57115e267a006cd058fe3e305 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1061,6 +1061,7 @@ config I2C_PXA_SLAVE config I2C_QCOM_CCI tristate "Qualcomm Camera Control Interface" depends on ARCH_QCOM || COMPILE_TEST + select MFD_SYSCON select PM_OPP help If you say yes to this option, support will be included for the diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 76a5dedf659fb8396ca5df188143469977526505..0e2190cf3300b7da727fc798a1440f30fa73e28d 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -7,11 +7,13 @@ #include #include #include +#include #include #include #include #include #include +#include #define CCI_HW_VERSION 0x0 #define CCI_RESET_CMD 0x004 @@ -137,9 +139,26 @@ struct cci { struct clk_bulk_data *clocks; int nclocks; struct clk *cci_clk; + /* Optional CCU output mux, routing the I2C ports to the CCI */ + struct regmap *ccu_mux; + u32 ccu_mux_reg; + u32 ccu_mux_mask; struct cci_master master[NUM_MASTERS]; }; +/* + * Hand the I2C ports over to the CCI. This has to be done with the CCI + * clocks enabled, which the mux register access needs, and before the CCI + * is reset or configured. + */ +static int cci_ccu_mux_select(struct cci *cci) +{ + if (!cci->ccu_mux) + return 0; + + return regmap_set_bits(cci->ccu_mux, cci->ccu_mux_reg, cci->ccu_mux_mask); +} + static irqreturn_t cci_isr(int irq, void *dev) { struct cci *cci = dev; @@ -651,6 +670,12 @@ static int __maybe_unused cci_resume_runtime(struct device *dev) if (ret) return ret; + ret = cci_ccu_mux_select(cci); + if (ret) { + cci_disable_clocks(cci); + return ret; + } + return cci_init(cci); } @@ -668,6 +693,7 @@ static int cci_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *r; + u32 mux_args[2]; struct cci *cci; int ret, i; u32 val; @@ -730,6 +756,18 @@ static int cci_probe(struct platform_device *pdev) if (IS_ERR(cci->base)) return PTR_ERR(cci->base); + cci->ccu_mux = syscon_regmap_lookup_by_phandle_args(dev->of_node, "qcom,ccu-mux-sel", + 2, mux_args); + if (IS_ERR(cci->ccu_mux)) { + ret = PTR_ERR(cci->ccu_mux); + if (ret != -ENOENT) + return dev_err_probe(dev, ret, "failed to get CCU mux\n"); + cci->ccu_mux = NULL; + } else { + cci->ccu_mux_reg = mux_args[0]; + cci->ccu_mux_mask = mux_args[1]; + } + /* Clocks */ ret = devm_clk_bulk_get_all(dev, &cci->clocks); @@ -761,6 +799,10 @@ static int cci_probe(struct platform_device *pdev) if (ret < 0) return ret; + ret = cci_ccu_mux_select(cci); + if (ret) + goto disable_clocks; + /* Interrupt */ ret = platform_get_irq(pdev, 0); -- 2.34.1