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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261105-rockchip-pcie-system-suspend-v9-4-a2e55846649e@collabora.com> References: <20261105-rockchip-pcie-system-suspend-v9-0-a2e55846649e@collabora.com> In-Reply-To: <20261105-rockchip-pcie-system-suspend-v9-0-a2e55846649e@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2814; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=SUw4+10Lg2ZDAwZtr18eSAbgDCoszLb8eKffkbMHfiU=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGrshZZHX1fso8CSlXsdPX5Wot4Rqt3hyBkqm e+BUJxaE3aAgokCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJq7IWWAAoJENju1/PI O/qa25IP/AnmzFH7BIEBRozskjOIUzAi2fB+sKjfW2cohgPpObSaPCzQPWczguR1eHyzPIGG/by gTA2FBaGVFF6MHHfYXXRFw6IBd0yXPmdUuhISXwa4y3o8IIpm8NielIgMmOZcQ6gRSs6PUnkJLd 3egh3iTOnYNH1Tcqw6LHXHvJBOFTmMWB4pCidLcKOhjujwHt6vJdXmbbkc3ijOO5oHXrk+F0DvJ 5dEdO7eB+j1LmVnexFz6AaVJ5wOM1NELjr6M8d2rNlrEePesErZtwobpzMlmF9a23Onm7tUJgKn nS2f32QuIcqsNisMv+hYfKvuamqaSQeZKTN95GDm8Xv7/n2jR8s7RdTR/21nBUXndqoLLkoEG0F uhDEaD9dxiGFcNRV671RvsowUSHNhSPSUPXJeQgXSKqC/tWziaBeq4eXBUgM8Bv0wJbm0cCGFDq R3jF/pBodrHE/i7SjOnNZiZHxl0yDbP+wJ1HWl/jbBwaGbm//WqYT6rrK9F25tO2lIq3Gullch5 YYwwse4r9Op8zIcGjieAZHc6NLbSimNJ4/6vxkVfHZDCAsqfDQJe/6DJ0BjeCrWJhkeq8RAjbLr tJZoohuq11q/xT6cBUIwjU1uG/EOq6ZdOvr+ExLQZOSX/vO96CXZ1oebEXBUv8M4xfAh6d8Lz0y +nWesW6GVgjR+IbR4388nGw== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Remove code duplication and improve readability by introducing a new function to setup the enhanced LTSSM mode. Reviewed-by: Shawn Lin Signed-off-by: Sebastian Reichel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 28 ++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index a3b0fb918479..92154a790ac0 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -683,6 +683,18 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) return IRQ_HANDLED; } +static void rockchip_pcie_enable_enhanced_ltssm_control_mode(struct rockchip_pcie *rockchip, + bool delay_link_training_after_reset) +{ + u32 val; + + /* Enable the enhanced control mode of signal app_ltssm_enable */ + val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); + if (delay_link_training_after_reset) + val |= FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1); + rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); +} + static int rockchip_pcie_configure_rc(struct platform_device *pdev, struct rockchip_pcie *rockchip) { @@ -706,9 +718,7 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev, return ret; } - /* LTSSM enable control mode */ - val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, false); rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC), @@ -765,13 +775,7 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev, return ret; } - /* - * LTSSM enable control mode, and automatically delay link training on - * hot reset/link-down reset. - */ - val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1) | - FIELD_PREP_WM16(PCIE_LTSSM_APP_DLY2_EN, 1); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, true); rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_EP), @@ -940,9 +944,7 @@ static int rockchip_pcie_rc_reset_root_port(struct pci_host_bridge *bridge, goto deinit_clk; } - /* LTSSM enable control mode */ - val = FIELD_PREP_WM16(PCIE_LTSSM_ENABLE_ENHANCE, 1); - rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); + rockchip_pcie_enable_enhanced_ltssm_control_mode(rockchip, false); rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_SET_MODE(PCIE_CLIENT_MODE_RC), -- 2.53.0