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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261105-rockchip-pcie-system-suspend-v9-7-a2e55846649e@collabora.com> References: <20261105-rockchip-pcie-system-suspend-v9-0-a2e55846649e@collabora.com> In-Reply-To: <20261105-rockchip-pcie-system-suspend-v9-0-a2e55846649e@collabora.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Philipp Zabel , Jingoo Han , Shawn Lin , Liam Girdwood , Mark Brown , "Yury Norov (NVIDIA)" , Nicolas Frattaroli Cc: Alexey Charkov , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3140; i=sebastian.reichel@collabora.com; h=from:subject:message-id; bh=Zuu47c5Rl5LpijQfd0h428pfqqmH6gW6BuU2h4/pz4A=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGrshZYw8YNoXWbCm5k9W3bBXqoP1EG7nVnn0 UthRW0K3YPCtokCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJq7IWWAAoJENju1/PI O/qaAnAP/RTmEXV+YSygiU4hYFEqUXwXbIfHoHC5JgBBrDccFfAsKgXPPGJuyz/NyzCwZhFPGVl DkdSK2tPwmhRVaQ7OhYSRukbHQ77g0OAU0U+BppXMVKnfFxcZVAEfo0yf7mDwtaLULskpBpJnh9 w7glBFZ/QmLDAkF2InaEp48NPsYLcBH5fYnal2cb7yDSUbZx+DljSe1eZk4i/y+/nbU7Lr8vq59 PZMRrOcOjTmsfhHObdmNLRy9VrKYot4/hTPmFswNEqe12TCkL56WdBADZuydX5PjSYsFVBHaxSF /EtdENvvRYSXgPpBhRnBkhRxLu3S+ZVjuIN9nTymajeRJarF64xDd/TayEV7HFq+NYS9m844NMd paCUXQrWKHrN4qUVYZAp8XfCHVHcuQBoo2+JewfrvZxzG5WcBC30eZZSNYZ0holpnjMqUNh6Xst N+5b24SH8zzKPPo3zpPvINQ+K1CkLYCvLcet7b1t3I5psFgNyahPa0gfcJMCyhbqmSVli2NcKiT AWkpPAKoxsVYBhOWvRJ+zKmjV3xZ2eniKDd3lqGwQe+uwBmOfFOpF5fwSYiuchMCyHbiwDd2zfH 4nD50o/4DrWPktiTs69y2gMgj/CEmBW5Ont8SCOFBCrizWcKsYrKT5Q4R588u+4trM+0M+Nua4z wNQ6AJ0BWU9meVX17Dyou8g== X-Developer-Key: i=sebastian.reichel@collabora.com; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Prepare Rockchip PCIe controller for system suspend support by adding the PME turn off operation. Reviewed-by: Shawn Lin Signed-off-by: Sebastian Reichel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 47 +++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index b4f53ce86079..d8968743732c 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -47,6 +47,10 @@ #define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1) #define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0) +/* Interrupt Status Register for Received Messages */ +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 +#define PME_TO_ACK BIT(9) + /* Interrupt Status Register Related to Legacy Interrupt */ #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 @@ -71,6 +75,11 @@ #define PCIE_CLKREQ_READY FIELD_PREP_WM16(BIT(0), 1) #define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0) #define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1) +#define PME_READY_ENTER_L23 BIT(3) + +/* Message Request Register */ +#define PCIE_CLIENT_MSG_GEN 0x34 +#define PME_TURN_OFF FIELD_PREP_WM16(BIT(4), 1) /* RASDES TBA information */ #define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154 @@ -439,8 +448,46 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); + struct device *dev = rockchip->pci.dev; + u32 status; + int ret; + + /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, + status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) { + dev_warn(dev, "Failed to send PME_Turn_Off\n"); + return; + } + + /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */ + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STATUS_MSG_RX, + status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) { + dev_warn(dev, "Failed to receive PME_TO_Ack\n"); + return; + } + + /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ + rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX); + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER_CON, + status, status & PME_READY_ENTER_L23, + PCIE_PME_TO_L2_TIMEOUT_US / 10, + PCIE_PME_TO_L2_TIMEOUT_US); + if (ret) + dev_err(dev, "Failed to get ready to enter L23 message\n"); +} + static const struct dw_pcie_host_ops rockchip_pcie_host_ops = { .init = rockchip_pcie_host_init, + .pme_turn_off = rockchip_pcie_pme_turn_off, }; /* -- 2.53.0