Re: [PATCH 1/2] dt-bindings: phy: Add Siflower SF19A2890 USB 2.0 PHY

[Conor Dooley <conor@kernel.org>]

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On Wed, Nov 04, 2026 at 07:39:32PM -0500, Joseph Telaak wrote:
> > > +        reg = <0x19e0c040 0x60>;
> >
> > That's a weird offset and size.
> > What lies in the regions around this device?
> 
> It sits in the 1 KiB from 0x19e0c000 up to the next block at
> 0x19e0c400. At 0x0, 0x4 and 0xc are the reset, clock gate and bus output
> enable registers of the USB clock and reset manager, which the clk
> series describes as siflower,sf19a2890-usb-crm; 0x8 holds a value I
> have no documentation for. The OpenWrt port gives the PHY 0x40-0x9f,
> and its driver only uses 0x44, the PHY's sleep control. Read from
> U-Boot, registers between 0x40 and 0x8f hold non-zero values I have no
> documentation for either, and the rest reads as 0. The GMAC's
> configuration registers sit the same way, at 0x40 past its clock and
> reset manager at 0x19e04400.
> 
> If you'd prefer one node for the whole region, providing the clocks,
> resets and the PHY, I'll restructure it that way for v2.

No, not asking for that. Just making sure this wasn't some sort of
syscon being hidden by the offsets and size.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable


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