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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-85f1dbb298fsm292276a34.6.2026.11.05.12.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 12:52:23 -0800 (PST) From: James Hilliard Date: Thu, 05 Nov 2026 13:52:07 -0700 Subject: [PATCH v8 06/11] serial: 8250_dw: derive RX trigger thresholds from the FIFO depth X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261105-submit-h616-uart-fifo-v1-v8-6-14024d2b184b@gmail.com> References: <20261105-submit-h616-uart-fifo-v1-v8-0-14024d2b184b@gmail.com> In-Reply-To: <20261105-submit-h616-uart-fifo-v1-v8-0-14024d2b184b@gmail.com> To: Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 DW_apb_uart uses receive thresholds of one byte, one quarter full, one half full and two bytes below full. The generic 16550A table describes these encodings only for a 16-byte FIFO. For example, the half-full setting on a 64-byte DW FIFO is reported as eight bytes instead of 32, and a sysfs request for 32 bytes selects the 62-byte encoding. Build a per-port threshold table from the discovered FIFO depth in dwlib and install receive-trigger callbacks for CPR-described FIFOs, including LPSS ports. Keep the setup helper available to integrations which obtain the depth without probing the optional DW registers. Validate that each threshold is positive and representable before constructing the table. Serialize FCR updates with termios and the port lock, acquire a runtime PM reference before accessing the device, and propagate resume errors without changing the shadow or hardware. Update only the trigger field so changing the threshold preserves the FIFO contents. The FCR mapping is documented in the DW_apb_uart databook, section 6, FIFO Control Register. The existing default FCR encoding is unchanged. Signed-off-by: James Hilliard --- drivers/tty/serial/8250/8250_dwlib.c | 88 ++++++++++++++++++++++++++++++++++++ drivers/tty/serial/8250/8250_dwlib.h | 2 + 2 files changed, 90 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c index 4a06dec6e263..004817cc8f28 100644 --- a/drivers/tty/serial/8250/8250_dwlib.c +++ b/drivers/tty/serial/8250/8250_dwlib.c @@ -1,18 +1,27 @@ // SPDX-License-Identifier: GPL-2.0+ /* Synopsys DesignWare 8250 library. */ +#include #include #include #include #include #include +#include #include +#include +#include #include #include #include #include "8250_dwlib.h" +/* DesignWare FIFO-relative receive thresholds */ +#define DW_UART_RXTRIG_QUARTER_DIV 4 +#define DW_UART_RXTRIG_HALF_DIV 2 +#define DW_UART_RXTRIG_FULL_MARGIN 2 + /* * divisor = div(I) + div(F) * "I" means integer, "F" means fractional @@ -208,11 +217,86 @@ static const struct serial_rs485 dw8250_rs485_supported = { SER_RS485_ADDR_DEST, }; +/* The trigger is the masked FCR receive trigger field, in register position */ +static unsigned int dw8250_rxtrig_bytes(struct uart_port *p, unsigned int trigger) +{ + switch (trigger) { + case UART_FCR_TRIGGER_1: + return 1; + case UART_FCR_TRIGGER_4: + return p->fifosize / DW_UART_RXTRIG_QUARTER_DIV; + case UART_FCR_TRIGGER_8: + return p->fifosize / DW_UART_RXTRIG_HALF_DIV; + default: + return p->fifosize - DW_UART_RXTRIG_FULL_MARGIN; + } +} + +static int dw8250_get_rxtrig(struct uart_port *p) +{ + struct dw8250_port_data *pd = p->private_data; + struct uart_8250_port *up = up_to_u8250p(p); + + guard(uart_port_lock_irqsave)(p); + + return pd->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; +} + +static int dw8250_set_rxtrig(struct uart_port *p, u16 bytes) +{ + struct dw8250_port_data *pd = p->private_data; + struct uart_8250_port *up = up_to_u8250p(p); + int fcr, ret; + + fcr = serial8250_bytes_to_fcr(pd->rxtrig_bytes, bytes); + if (fcr < 0) + return fcr; + + guard(mutex)(&p->state->port.mutex); + + PM_RUNTIME_ACQUIRE_IF_ENABLED(p->dev, pm); + ret = PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret) + return ret; + + guard(uart_port_lock_irqsave)(p); + + up->fcr &= ~UART_FCR_TRIGGER_MASK; + up->fcr |= fcr; + /* Changing the trigger alone preserves the FIFO contents */ + serial_port_out(p, UART_FCR, up->fcr); + + return 0; +} + +int dw8250_setup_rxtrig(struct uart_port *p) +{ + struct dw8250_port_data *pd = p->private_data; + + /* Each FIFO-relative threshold must be positive and fit in the table */ + if (p->fifosize < DW_UART_RXTRIG_QUARTER_DIV || + p->fifosize - DW_UART_RXTRIG_FULL_MARGIN > U16_MAX) + return dev_err_probe(p->dev, -EINVAL, + "invalid FIFO size %u\n", p->fifosize); + + for (unsigned int i = 0; i < ARRAY_SIZE(pd->rxtrig_bytes); i++) { + unsigned int trigger = FIELD_PREP(UART_FCR_TRIGGER_MASK, i); + + pd->rxtrig_bytes[i] = dw8250_rxtrig_bytes(p, trigger); + } + p->get_rxtrig = dw8250_get_rxtrig; + p->set_rxtrig = dw8250_set_rxtrig; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(dw8250_setup_rxtrig, "SERIAL_8250"); + int dw8250_setup_port(struct uart_port *p) { struct dw8250_port_data *pd = p->private_data; struct uart_8250_port *up = up_to_u8250p(p); u32 reg, old_dlf; + int ret; pd->hw_rs485_support = dw8250_detect_rs485_hw(p); if (pd->hw_rs485_support) { @@ -258,6 +342,10 @@ int dw8250_setup_port(struct uart_port *p) p->flags |= UPF_FIXED_TYPE; p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); up->capabilities = UART_CAP_FIFO | UART_CAP_NOTEMT; + + ret = dw8250_setup_rxtrig(p); + if (ret) + return ret; } if (reg & DW_UART_CPR_AFCE_MODE) diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h index 4d32651956ab..b896dd9bebb7 100644 --- a/drivers/tty/serial/8250/8250_dwlib.h +++ b/drivers/tty/serial/8250/8250_dwlib.h @@ -86,6 +86,7 @@ struct dw8250_port_data { struct uart_8250_dma dma; /* Hardware configuration */ + u16 rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE]; u32 cpr_value; u8 dlf_size; @@ -100,6 +101,7 @@ struct dw8250_port_data { unsigned int dw8250_get_divisor_dlf(struct uart_port *p, unsigned int baud, unsigned int *frac); void dw8250_set_divisor_dlf(struct uart_port *p, unsigned int quot_frac); void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, const struct ktermios *old); +int dw8250_setup_rxtrig(struct uart_port *p); int dw8250_setup_port(struct uart_port *p); static inline u32 dw8250_readl_ext(struct uart_port *p, int offset) -- 2.53.0