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([39.170.101.209]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b0b312cc44sm2293530a91.1.2026.11.04.21.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2026 21:53:53 -0800 (PST) From: Ping Li To: yin.li@oss.qualcomm.com Cc: robh@kernel.org, james.morse@arm.com, ben.horgan@arm.com, sdonthineni@nvidia.com, andre.przywara@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ping Li Subject: Re: [PATCH v4 0/6] arm-mpam: Add basic device tree support for resctrl Date: Thu, 5 Nov 2026 13:53:47 +0800 Message-Id: <20261105055347.947416-1-leeonion.muyu@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <9d370f12-9e4c-4b80-9d28-ff8085ce3aee@oss.qualcomm.com> References: <20261028-mpam-resctrl-dt-knp-support-v4-0-bdda1e445cba@oss.qualcomm.com> <20261104081302.304667-1-leeonion.muyu@gmail.com> <9d370f12-9e4c-4b80-9d28-ff8085ce3aee@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Yin, Sure. Our memory controller MSC is described as a top-level node. The MPAM register window is mapped independently in the SoC (the component sits on the DDR egress path rather than being a sub-block of a memory-controller DT node), so the node is a direct child of the root: ddr_msc: msc@2238000 { compatible = ",-ddr-qos", "arm,mpam-memory-controller-msc", "arm,mpam-msc"; reg = <0x0 0x02238000 0x0 0x1000>; arm,not-ready-us = <10>; }; The first compatible in the list is for our platform glue; I have replaced it with a placeholder here since it is not relevant to the binding discussion. Notes on the properties, in case they matter for the binding: - reg: the MPAM register window. Only a subset of the architectural register space is implemented, so the size is the truncated window. - single RIS: the component reports HAS_RIS=0, so there are no ris@N child nodes. - no interrupts: the component has no MPAM ESR block, so there is no interrupts property. - arm,not-ready-us: 10. The verified probe path: the node matches via "arm,mpam-msc", and patch 6/8 in v3 classifies it as MPAM_CLASS_MEMORY and treats it as accessible from all CPUs, which is exactly the behavior we need. One question in return: with the node being a direct child of the root rather than a child of a memory-controller node, is that a form the binding should cover? If the binding expects the MSC to always be a sub-node of a memory controller, we would need the top-level form to be allowed as well. Thanks, Ping Li