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Add cqspi_memcpy_fromio() to handle non-DMA transfers, using 2-byte-aligned I/O reads for 8D-8D-8D mode to satisfy the minimum 16-bit AHB transaction width required by the Cadence OSPI controller in that mode. Change cqspi_direct_read_execute() to take the full spi_mem_op and post_config_max_speed_hz instead of separate buf/from/len parameters, matching the interface needed by the PHY-aware version in the following patch. Thread post_config_max_speed_hz from cqspi_mem_process() through cqspi_read(). Transfers shorter than CQSPI_PHY_MIN_DIRECT_READ_LEN bytes always use the memcpy path; longer transfers use DMA when available. Tested-by: Srikanth Boyapally Tested-by: Moteen Shah Reviewed-by: Moteen Shah Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 76 +++++++++++++++++++++++++++---- 1 file changed, 66 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 7993029207e9..c324451a9a28 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -30,6 +30,7 @@ #include #include #include +#include #define CQSPI_NAME "cadence-qspi" #define CQSPI_MAX_CHIPSELECT 4 @@ -155,6 +156,8 @@ struct cqspi_driver_platdata { #define CQSPI_READ_TIMEOUT_MS 10 #define CQSPI_BUSYWAIT_TIMEOUT_US 500 #define CQSPI_DLL_TIMEOUT_US 300 +/* Minimum transfer length to use DMA for direct reads */ +#define CQSPI_PHY_MIN_DIRECT_READ_LEN 17 /* Runtime_pm autosuspend delay */ #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 @@ -1528,8 +1531,8 @@ static void cqspi_rx_dma_callback(void *param) complete(&cqspi->rx_dma_complete); } -static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, - u_char *buf, loff_t from, size_t len) +static int cqspi_direct_read_dma(struct cqspi_flash_pdata *f_pdata, u_char *buf, + loff_t from, size_t len) { struct cqspi_st *cqspi = f_pdata->cqspi; struct device *dev = &cqspi->pdev->dev; @@ -1541,11 +1544,6 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, dma_addr_t dma_dst; struct device *ddev; - if (!cqspi->rx_chan || !virt_addr_valid(buf)) { - memcpy_fromio(buf, cqspi->ahb_base + from, len); - return 0; - } - ddev = dmaengine_get_dma_device(cqspi->rx_chan); dma_dst = dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); if (dma_mapping_error(ddev, dma_dst)) { @@ -1587,8 +1585,64 @@ static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, return ret; } +static void cqspi_memcpy_fromio(const struct spi_mem_op *op, void *to, + const void __iomem *from, size_t count) +{ + if (op->data.buswidth == 8 && op->data.dtr) { + /* Handle unaligned start with 2-byte read */ + if (count && !IS_ALIGNED((unsigned long)from, 4)) { + put_unaligned(__raw_readw(from), (u16 *)to); + from += 2; + to += 2; + count -= 2; + } + + /* + * Use an explicit 32-bit read loop for the bulk; this + * guarantees the minimum 16-bit AHB transaction width required + * in 8D-8D-8D mode on all architectures. Pairing the + * endian-agnostic __raw_read*() with native put_unaligned() + * (rather than put_unaligned_le*()) preserves the byte stream + * exactly as memcpy_fromio() would, on both LE and BE hosts. + */ + while (count >= 4) { + put_unaligned(__raw_readl(from), (u32 *)to); + from += 4; + to += 4; + count -= 4; + } + + /* Handle remaining 2 bytes */ + if (count) + put_unaligned(__raw_readw(from), (u16 *)to); + + return; + } + + memcpy_fromio(to, from, count); +} + +static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op, + u32 post_config_max_speed_hz) +{ + struct cqspi_st *cqspi = f_pdata->cqspi; + loff_t from = op->addr.val; + size_t len = op->data.nbytes; + u_char *buf = op->data.buf.in; + + if (!cqspi->rx_chan || !virt_addr_valid(buf) || + len < CQSPI_PHY_MIN_DIRECT_READ_LEN) { + cqspi_memcpy_fromio(op, buf, cqspi->ahb_base + from, len); + return 0; + } + + return cqspi_direct_read_dma(f_pdata, buf, from, len); +} + static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op) + const struct spi_mem_op *op, + u32 post_config_max_speed_hz) { struct cqspi_st *cqspi = f_pdata->cqspi; const struct cqspi_driver_platdata *ddata = cqspi->ddata; @@ -1604,7 +1658,8 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, if ((cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) || (cqspi->ddata && cqspi->ddata->quirks & CQSPI_NO_INDIRECT_MODE)) - return cqspi_direct_read_execute(f_pdata, buf, from, len); + return cqspi_direct_read_execute(f_pdata, op, + post_config_max_speed_hz); if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) == 0)) @@ -1632,7 +1687,8 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) !cqspi->disable_stig_mode)) return cqspi_command_read(f_pdata, op); - return cqspi_read(f_pdata, op); + return cqspi_read(f_pdata, op, + mem->spi->post_config_max_speed_hz); } if (!op->addr.nbytes || !op->data.buf.out) -- 2.34.1