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Add cqspi_tune_phy_write() to toggle PHY mode around the write, mirroring cqspi_tune_phy_read() but leaving PHY_PIPELINE clear -- that bit only affects read data capture and must not be set during writes. PHY is used only when cqspi_use_tuned_phy() confirms the op in hand is running at the calibrated post-config rate, the same check already used on the read side. This restricts PHY writes to NAND devices where a write op template was provided to execute_tuning and subsequent writes reuse that same template; NOR flash writes are unaffected. The indirect write is cancelled before disabling PHY in the error path so that cqspi_wait_idle() inside cqspi_tune_phy_write() does not time out while the controller is still waiting for AHB data. Thread post_config_max_speed_hz from cqspi_mem_process() through cqspi_write() into cqspi_indirect_write_execute() for the frequency check. Tested-by: Srikanth Boyapally Tested-by: Moteen Shah Reviewed-by: Moteen Shah Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 69 +++++++++++++++++++++++++++---- 1 file changed, 62 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 55c446f4245a..806bf49e814d 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -159,6 +160,8 @@ struct cqspi_driver_platdata { #define CQSPI_DLL_TIMEOUT_US 300 /* Minimum transfer length to use DMA for direct reads */ #define CQSPI_PHY_MIN_DIRECT_READ_LEN 17 +/* Minimum indirect write length to amortize PHY enable/disable overhead */ +#define CQSPI_PHY_MIN_INDIRECT_WRITE_LEN SZ_1K /* Runtime_pm autosuspend delay */ #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 @@ -1175,6 +1178,37 @@ static int cqspi_tune_phy_read(struct cqspi_flash_pdata *f_pdata, bool enable) return ret; } +static int cqspi_tune_phy_write(struct cqspi_flash_pdata *f_pdata, bool enable) +{ + struct cqspi_st *cqspi = f_pdata->cqspi; + void __iomem *reg_base = cqspi->iobase; + unsigned int reg; + int ret; + + if (!enable) { + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg &= ~(CQSPI_REG_CONFIG_PHY_EN | CQSPI_REG_CONFIG_PHY_PIPELINE); + writel(reg, reg_base + CQSPI_REG_CONFIG); + return cqspi_wait_idle(cqspi); + } + + ret = cqspi_wait_idle(cqspi); + if (ret) + return ret; + + ret = cqspi_phy_reprogram_dll(f_pdata); + if (ret) + return ret; + + /* PHY_PIPELINE is for read capture; must not be set during writes. */ + reg = readl(reg_base + CQSPI_REG_CONFIG); + reg |= CQSPI_REG_CONFIG_PHY_EN; + reg &= ~CQSPI_REG_CONFIG_PHY_PIPELINE; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + return 0; +} + static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx) @@ -1366,7 +1400,7 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, loff_t to_addr, const u8 *txbuf, - const size_t n_tx) + const size_t n_tx, bool use_phy) { struct cqspi_st *cqspi = f_pdata->cqspi; struct device *dev = &cqspi->pdev->dev; @@ -1378,6 +1412,12 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (!refcount_read(&cqspi->refcount)) return -ENODEV; + if (use_phy) { + ret = cqspi_tune_phy_write(f_pdata, true); + if (ret) + return ret; + } + writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR); writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); @@ -1454,17 +1494,28 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR); - cqspi_wait_idle(cqspi); + ret = cqspi_wait_idle(cqspi); - return 0; + if (use_phy) + ret = cqspi_tune_phy_write(f_pdata, false) ?: ret; + + return ret; failwr: /* Disable interrupt. */ writel(0, reg_base + CQSPI_REG_IRQMASK); - /* Cancel the indirect write */ + /* + * Cancel the indirect write before disabling PHY so that + * cqspi_wait_idle() inside cqspi_tune_phy_write() does not time out + * while the controller is still waiting for AHB data. + */ writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, reg_base + CQSPI_REG_INDIRECTWR); + + if (use_phy) + cqspi_tune_phy_write(f_pdata, false); + return ret; } @@ -1602,12 +1653,14 @@ static bool cqspi_use_tuned_phy(struct cqspi_flash_pdata *f_pdata, } static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op) + const struct spi_mem_op *op, + u32 post_config_max_speed_hz) { struct cqspi_st *cqspi = f_pdata->cqspi; loff_t to = op->addr.val; size_t len = op->data.nbytes; const u_char *buf = op->data.buf.out; + bool use_phy; int ret; ret = cqspi_write_setup(f_pdata, op); @@ -1629,7 +1682,9 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, return cqspi_wait_idle(cqspi); } - return cqspi_indirect_write_execute(f_pdata, to, buf, len); + use_phy = len >= CQSPI_PHY_MIN_INDIRECT_WRITE_LEN && + cqspi_use_tuned_phy(f_pdata, op, post_config_max_speed_hz); + return cqspi_indirect_write_execute(f_pdata, to, buf, len, use_phy); } static void cqspi_rx_dma_callback(void *param) @@ -1857,7 +1912,7 @@ static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op *op) if (!op->addr.nbytes || !op->data.buf.out) return cqspi_command_write(f_pdata, op); - return cqspi_write(f_pdata, op); + return cqspi_write(f_pdata, op, mem->spi->post_config_max_speed_hz); } static int cqspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) -- 2.34.1