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DQS mode uses a dedicated strobe signal for improved timing margins in high-speed SPI modes. Reviewed-by: Miquel Raynal Tested-by: Srikanth Boyapally Tested-by: Moteen Shah Reviewed-by: Moteen Shah Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index c2c6105798e1..4be37081d066 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -192,6 +192,7 @@ struct cqspi_driver_platdata { #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF +#define CQSPI_REG_READCAPTURE_DQS_LSB 8 #define CQSPI_REG_SIZE 0x14 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 @@ -458,7 +459,7 @@ static int cqspi_wait_idle(struct cqspi_st *cqspi) } static void cqspi_readdata_capture(struct cqspi_st *cqspi, const bool bypass, - const unsigned int delay) + const bool dqs, const unsigned int delay) { void __iomem *reg_base = cqspi->iobase; unsigned int reg; @@ -476,6 +477,11 @@ static void cqspi_readdata_capture(struct cqspi_st *cqspi, const bool bypass, reg |= (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) << CQSPI_REG_READCAPTURE_DELAY_LSB; + if (dqs) + reg |= BIT(CQSPI_REG_READCAPTURE_DQS_LSB); + else + reg &= ~BIT(CQSPI_REG_READCAPTURE_DQS_LSB); + writel(reg, reg_base + CQSPI_REG_READCAPTURE); } @@ -1316,7 +1322,7 @@ static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, cqspi->sclk = sclk; cqspi_config_baudrate_div(cqspi); cqspi_delay(f_pdata); - cqspi_readdata_capture(cqspi, !cqspi->rclk_en, + cqspi_readdata_capture(cqspi, !cqspi->rclk_en, false, f_pdata->read_delay); } -- 2.34.1