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Thu, 5 Nov 2026 04:32:51 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Thu, 5 Nov 2026 04:32:47 -0800 From: Sumit Gupta To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH] cpufreq: CPPC: Set CPPC Enable register in cpu_init Date: Thu, 5 Nov 2026 18:02:44 +0530 Message-ID: <20261105123244.3132560-1-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH4PEPF0000B60A:EE_|BL1PR12MB5993:EE_ X-MS-Office365-Filtering-Correlation-Id: 43e603ef-3b23-4e3e-4676-08df3b38f202 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|376014|7416014|36860700016|82310400026|261026140227099003|11063799006|56012099006|261028144727099003|261009223027099003|261021121427099003|261022105027099003|10067099003|18002099003|261102123227099003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: orti8AEFVg1gX7ZvbBoZ84256WTLmvuX0iCzT4jMzI8yvkvJl5OoitYWcN3FNwJUKDl9wPGZ4ZWcjF6sVN2ROXBF8okWb0NzxjZQShPljlq5f/uYB1g5amVoJkh/EZWzX4Jqg/CU75UwhGu0GwaniY40WYRhB+LRMGPwf1r0WCkZAO/Whm3199hVXRVY5noSubMIYmApZ6xehu6qTmYL9TT2jpfo1j8ulR/8AvjcDniYjvxflNXoazMrPlU3l7Yk70eOOY7fTPqd6f3q0g6S8x4rjM3Wn9QtfU7yC0CxbhnfcV/K/qExnMzVXCrFAB9/H2rf0Wf4qSC5MXC82ysr30K0Ad1VZnkddS/IEAI//cuS2tJ3XY1c66Azro9v4YhmkONGyob3XJV1fZpc5Tk7Qvjo/mnpNtUBGl/pFHPOUmz7jAakbvbH6V+h5TW2p98S X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2026 12:33:07.3455 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43e603ef-3b23-4e3e-4676-08df3b38f202 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: PH4PEPF0000B60A.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5993 As per ACPI 6.x s8.4.6.1.4 (CPPC Enable register): "If supported by the platform, OSPM writes a one to this register to enable CPPC on this processor. If not implemented, OSPM assumes the platform always has CPPC enabled." The driver never writes this register. Call cppc_set_enable() at the start of cppc_cpufreq_cpu_init(). Errors are logged but not fatal, as the register is optional. Fixes: 5477fb3bd1e8 ("ACPI / CPPC: Add a CPUFreq driver for use with CPPC") Cc: stable@vger.kernel.org # v6.16+ Signed-off-by: Sumit Gupta --- Sending this separately from the autonomous mode boot parameter series where it was patch 1/2, as it is an independent bug fix. v5 of the series: https://lore.kernel.org/lkml/20260623080652.3353386-1-sumitg@nvidia.com/ drivers/cpufreq/cppc_cpufreq.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 957fa7775260..b8f4399b6e0b 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -679,6 +679,14 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) caps = &cpu_data->perf_caps; policy->driver_data = cpu_data; + /* + * Enable CPPC. The Enable register is optional - some platforms + * may not support it. + */ + ret = cppc_set_enable(cpu, true); + if (ret && ret != -EOPNOTSUPP) + pr_warn("Failed to enable CPPC for CPU%u (%d)\n", cpu, ret); + /* * Set min to lowest nonlinear perf to avoid any efficiency penalty (see * Section 8.4.7.1.1.5 of ACPI 6.1 spec) -- 2.34.1