[PATCH 5/8] pwm: fsl-ftm: Enable ipg_clk around regcache_sync() during resume

[Lee Jones <lee@kernel.org>]

On SoCs with a dedicated IP interface clock (ipg_clk), register accesses
require ipg_clk to be enabled in addition to the ftm_sys clock managed
by regmap_mmio.  In fsl_pwm_resume(), ipg_clk is only enabled inside the
channel loop for channels with PWMF_REQUESTED set, so if no channels are
currently requested, regcache_sync() writes to the hardware registers
while ipg_clk is disabled.

Enable ipg_clk across fsl_pwm_resume() around regcache_sync(), matching
fsl_pwm_init().

Fixes: 82a9c55a2bb0 ("pwm: fsl-ftm: Added a dedicated IP interface clock")
Closes: https://sashiko.dev/#/bug/linux-858851cf-55a9-4776-883c-69c05f3961f2
Cc: stable@vger.kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>
---
 drivers/pwm/pwm-fsl-ftm.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 35406b2e1925..9e5470e2efe6 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -501,8 +501,13 @@ static int fsl_pwm_resume(struct device *dev)
 {
 	struct pwm_chip *chip = dev_get_drvdata(dev);
 	struct fsl_pwm_chip *fpc = to_fsl_chip(chip);
+	int ret;
 	int i;
 
+	ret = clk_prepare_enable(fpc->ipg_clk);
+	if (ret)
+		return ret;
+
 	for (i = 0; i < chip->npwm; i++) {
 		struct pwm_device *pwm = &chip->pwms[i];
 
@@ -522,6 +527,8 @@ static int fsl_pwm_resume(struct device *dev)
 	regcache_cache_only(fpc->regmap, false);
 	regcache_sync(fpc->regmap);
 
+	clk_disable_unprepare(fpc->ipg_clk);
+
 	return 0;
 }
 #endif
Cc: shenwei.wang@nxp.com
-- 
2.56.0.398.g882cbad275-goog