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[159.2.239.150]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5eca8d77c6esm5043981e0c.6.2026.11.05.10.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 10:32:22 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1xP2G6-00000003Ng9-0h1l; Thu, 05 Nov 2026 14:32:22 -0400 Date: Thu, 5 Nov 2026 14:32:22 -0400 From: Jason Gunthorpe To: Tan Chi Cc: gong.shuai@sanechips.com.cn, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, anup@brainfault.org, atish.patra@linux.dev, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pbonzini@redhat.com, seanjc@google.com, kevin.tian@intel.com, andrew.jones@oss.qualcomm.com, fangyu.yu@linux.alibaba.com, wu.fei9@sanechips.com.cn, zhao.qingye@sanechips.com.cn, gsh517025@gmail.com Subject: Re: [RFC PATCH v2 9/9] iommu/riscv: Add riscv_iommu_attach_dev_nested Message-ID: <20261105183222.GE663069@ziepe.ca> References: <20261029061131.584453-10-gong.shuai@sanechips.com.cn> <20261105144944.10193-1-tanchi25@mails.ucas.ac.cn> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261105144944.10193-1-tanchi25@mails.ucas.ac.cn> On Thu, Nov 05, 2026 at 10:49:44PM +0800, Tan Chi wrote: > Hi Shuai and Fei, > > I noticed a potential issue with fixing the physical DC's PSCID to 0. > > In QEMU, different VFIO devices can have separate stage-1 HWPTs while > sharing the same vIOMMU and stage-2 parent. This means two devices may > have different first-stage page table roots but the same host GSCID > and PSCID=0. > > According to the RISC-V IOMMU specification, DC.ta.PSCID identifies > the first-stage address space when PDTV=0 and the first stage is not > Bare. Could this cause the physical IOMMU to reuse cached translations > across different stage-1 address spaces? Even broader invalidations > would not prevent such cache aliasing. > > There also seems to be a related issue in patch 6. > riscv_viommu_cache_invalidate() unconditionally forces PSCV=1 and > PSCID=0. However, an IOTINVAL.VMA with PSCV=0 also invalidates global > mappings, while PSCV=1 excludes them. This appears to narrow the > guest's requested invalidation scope and could leave stale global > translations cached. > > One possible approach might be to use the PSCID from the guest-provided > DC.ta when allocating the nested domain, and preserve the guest's PSCID > and PSCV settings during invalidation while substituting the host GSCID. > I'm not sure whether additional considerations are needed for PSCID > reuse or domain lifetime, though. If the guest is issuing invalidations you must always preserve the guests "ASID" or whatever your HW calls it. It can be virtualized and mapped from a guest view to physical, but it must be preserved and physical must be 1:1 with virtual. Jason