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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b0944eb1d1sm5492749a91.0.2026.11.05.12.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 12:41:19 -0800 (PST) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Nico Angelo Dela Cruz , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 13/15] drm/msm/a8xx: Use CP_PROTECT_PIPE regs Date: Thu, 5 Nov 2026 12:29:39 -0800 Message-ID: <20261105203057.66520-14-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261105203057.66520-1-robin.clark@oss.qualcomm.com> References: <20261105203057.66520-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDA4MiBTYWx0ZWRfXwa9IBiIiU/Jk KeGUvYu04DUfm2p2G6fz6wn23WJNhINyUzsafsB8aou/J35i66ixuACQKbQne8a0oe9IqVJJUCV oL/Pc3/GKNMvfd9qbvD974OW8RDRZi7LwJIjc57gCLSk/vYdgOpm8jc1xdH/sj2v+rEeuVa+N5Z k2aD9lnFCffGmEndHDhQ2csZalpVNRg0McrwXjJ+yIk5emWI3FLA0Lh3yQGpDizw7Q1Yv6AqBLZ cN9fFe+R7WbpUHLgkuLiO0gi3pTO9zfZ9q5LYGqG9wd6emtIFX8qLQKzAevomC/ymYrpPQP0X3J +wPibK+OIu2q4Zs07nhMLLXa7bQcZzRkv+96Kzs79O5rpA4To2hFIbgMZCGxky7RakUjV+aO184 ww9sKqkYJj6aW1uu7+sfd+Z/iyxfF7bJT4N9Ob5iEakL28VtEQLATqzh3B3hJ0yK6z4dcUlbUMp Y0rECjSyo2OZYS9PumA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDA4MiBTYWx0ZWRfX6oycFYBRhewx JgT1TANqURedcbDYmAoa73VoCZLtc/HzwH2PT67AC/MTK35ks6wB5jlOCiaj5u94AawLLfzPiTM /+FhDaR0VmkDgEATYJCPBbcfZKysyVI= X-Proofpoint-ORIG-GUID: bxNEYoA78WDdfwX5HR0qW5JTfkdo2XXY X-Authority-Analysis: v=2.4 cv=a4+lZkSF c=1 sm=1 tr=0 ts=6aece9f3 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=UnxhJFuZtzOLgjs1IeAA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: bxNEYoA78WDdfwX5HR0qW5JTfkdo2XXY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_05,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 adultscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611050082 If there are not enough global CP_PROTECT_GLOBAL regs, we can use CP_PROTECT_PIPE regs for the extra spans. We just need to configure them the same on all pipes. Tested-by: Alexander Koskovich # Milos (Nothing Phone 3a) Reviewed-by: Konrad Dybcio Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index f65bf82e5c21..f6afa5b3b0bb 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -261,12 +261,21 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) a8xx_aperture_clear(gpu); - for (i = 0; i < protect->count; i++) { + for (i = 0; i < min(64, protect->count); i++) { /* Intentionally skip writing to some registers */ - if (protect->regs[i]) { - gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); - final_cfg = protect->regs[i]; - } + if (!protect->regs[i]) + continue; + gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); + final_cfg = protect->regs[i]; + } + + for (; i < protect->count; i++) { + /* Intentionally skip writing to some registers */ + if (!protect->regs[i]) + continue; + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(i - 64), protect->regs[i]); + final_cfg = protect->regs[i]; } /* -- 2.56.0