From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@vger.kernel.org
Cc: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Paul Burton" <paulburton@kernel.org>,
"Paul Cercueil" <paul@crapouillou.net>,
"Stephen Boyd" <sboyd@kernel.org>,
"Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
linux-kernel@vger.kernel.org (open list),
linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK),
"H. Nikolaus Schaller" <hns@goldelico.com>,
"Paul Boddie" <paul@boddie.org.uk>
Subject: [PATCH 3/3] MIPS: CI20: Enable SMP with two CPUs
Date: Thu, 5 Nov 2026 12:32:42 -0800 [thread overview]
Message-ID: <20261105203243.2292647-4-f.fainelli@gmail.com> (raw)
In-Reply-To: <20261105203243.2292647-1-f.fainelli@gmail.com>
From: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Enable both JZ4780 cores now that the generic Ingenic platform provides
secondary CPU reset and mailbox support. The existing device tree
already reserves TCU channels for both per-CPU clock events.
Rebase Zhou Yanjie's original defconfig update onto the current CI20
configuration. The resulting image brought up both cores on the board.
The rebase and validation used Codex assistance.
Link: https://lists.openwall.net/linux-kernel/2020/05/19/739
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/mips/configs/ci20_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index 90536cab417e..09d65094b1bd 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -22,6 +22,8 @@ CONFIG_EXPERT=y
CONFIG_MACH_INGENIC_SOC=y
CONFIG_JZ4780_CI20=y
CONFIG_HIGHMEM=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
CONFIG_HZ_100=y
# CONFIG_SUSPEND is not set
# CONFIG_SECCOMP is not set
--
2.53.0
next prev parent reply other threads:[~2026-11-05 20:32 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 20:32 [PATCH 0/3] " Florian Fainelli
2026-11-05 20:32 ` [PATCH 1/3] clk: ingenic: Poll JZ4780 CPU1 power status atomically Florian Fainelli
2026-11-06 9:11 ` Paul Cercueil
2026-11-05 20:32 ` [PATCH 2/3] MIPS: Ingenic: Add JZ4780 SMP support to the generic platform Florian Fainelli
2026-11-06 11:07 ` Paul Cercueil
2026-11-06 12:10 ` H. Nikolaus Schaller
2026-11-06 14:36 ` H. Nikolaus Schaller
2026-11-05 20:32 ` Florian Fainelli [this message]
2026-11-06 11:00 ` [PATCH 0/3] MIPS: CI20: Enable SMP with two CPUs H. Nikolaus Schaller
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