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Thu, 05 Nov 2026 13:07:43 -0800 (PST) Received: from letov ([62.41.24.155]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6b55ac6d032sm1966949a12.25.2026.11.05.13.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 13:07:43 -0800 (PST) From: Alexander Letuchiy To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Alexander Letuchiy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org Subject: [PATCH 4/5] arm64: dts: mediatek: Add MT6895 SoC Date: Fri, 6 Nov 2026 00:06:02 +0300 Message-ID: <20261105210622.523747-5-asalde.le1@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261105210622.523747-1-asalde.le1@gmail.com> References: <20261105210622.523747-1-asalde.le1@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add initial support for the MediaTek MT6895 (Dimensity 8100) SoC, which has four Cortex-A55 and four Cortex-A78 cores. Describe the CPUs, PSCI, the GICv3 interrupt controller, the architected timer, two UARTs and the watchdog. There is no clock controller driver for this SoC yet, so both UART clocks use a fixed 26 MHz clock. Signed-off-by: Alexander Letuchiy --- arch/arm64/boot/dts/mediatek/mt6895.dtsi | 166 +++++++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6895.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6895.dtsi b/arch/arm64/boot/dts/mediatek/mt6895.dtsi new file mode 100644 index 000000000000..c80f30da7bf9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6895.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include + +/ { + compatible = "mediatek,mt6895"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + + core6 { + cpu = <&cpu6>; + }; + + core7 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x400>; + enable-method = "psci"; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x500>; + enable-method = "psci"; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x600>; + enable-method = "psci"; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x700>; + enable-method = "psci"; + }; + }; + + clk26m: clock-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + #interrupt-cells = <4>; + interrupt-controller; + interrupts = ; + }; + + uart0: serial@11001000 { + compatible = "mediatek,mt6895-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11002000 { + compatible = "mediatek,mt6895-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + watchdog: watchdog@1c007000 { + compatible = "mediatek,mt6895-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x1c007000 0 0x100>; + }; + }; +}; -- 2.56.0