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Thu, 5 Nov 2026 13:17:02 -0800 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Thu, 5 Nov 2026 13:16:56 -0800 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Andrea Parri , Boris Pismenny , Cosmin Ratiu , Dragos Tatulea , "Gal Pressman" , Jeroen Massar , Jianbo Liu , Kuniyuki Iwashima , Leon Romanovsky , open list , , Mark Bloch , "Patrisious Haddad" , Prathamesh Deshpande , Raed Salem , Roi Dayan , Saeed Mahameed , Shay Drory , Simon Horman , Steffen Klassert , Tariq Toukan Subject: [PATCH net V3 0/8] net/mlx5e: Fix offload lifetime and exclusion bugs Date: Thu, 5 Nov 2026 23:16:28 +0200 Message-ID: <20261105211637.1083978-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000166C1:EE_|IA1PR12MB6235:EE_ X-MS-Office365-Filtering-Correlation-Id: 893ad6e3-076e-4606-c4d0-08df3b822d06 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|1800799024|36860700016|376014|23010399003|56012099006|10067099003|261102123227099003|13003099007|18002099003|261009223027099003|261021121427099003|261021123027099003|261022105027099003|261022075727099003|11063799006|261028144727099003|261026140227099003; X-Microsoft-Antispam-Message-Info: EFe8EoHYjzOYimxFYSamxJsY+WWLHhhnYAGPHOk2YziZUMdZeiX6frj+xh75wAptSVOhAw5w9UwK8G0uCyEXMqWjiXG6MUK25yAteUYvv0vDdUvJ2TpgwJ5Dg0EaSrBvsKFjo4lzT+ieqA/m7ggGYV9azdrKv3OMRBq2RBTTjGUNLBZ8CMM8V58efc6U2nSb6ZkTlZE7eN0N8+1rhuaohKBEV/1W6U14gcZ5WShBQHEz9D/Hz8IAxGquk/1U9+kqkBaMBKCw8XkbNa4nUgcgn2pnLho+Mi3QBOXgffoLwX4CS4ux7j2JVIFyMX+WW+HJT6iEHzp3VfRjRWqH6VumEC3HZNcKFZRPGz2HvzNynlNPypIguD2DV/AwTKhmakOkpOFZh7ydWuG053/+A84jCvMTxIamDGmga5GW3q52hn5EF6/xy429Zg/xAQQ7AmBGo2kUAknsthUNAeyuSenkhbQi+1vVgOIgwZDCwhC6Ny7MX0pgMYcKvr0aorsKZwAffjI5m1up98PQr5ieA+4cHSKm9QzHjRD1kson1sQ6902TrdawbPMBsOb/k9vzUKHELlGmVWFgEI7zaCJGrCyUcGOobQfASBTr4XqwQj/tu0xwVny3P8id0CsnXveKDPMnLgzhT2BWaLQsGMSylId3hD9s8UPFqFWXugqVqWcFAsnrU1sErCvvbFTlxZFcr95QfAg/IsjurrFP6mRaN8FdQQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(1800799024)(36860700016)(376014)(23010399003)(56012099006)(10067099003)(261102123227099003)(13003099007)(18002099003)(261009223027099003)(261021121427099003)(261021123027099003)(261022105027099003)(261022075727099003)(11063799006)(261028144727099003)(261026140227099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BbEqEZ01GY9JRx8CWsIlzTG4Vc+T6zlw9LpGi1dxKgAMf3cQQQGI7qUnhQZp6Doj+Q9i7KWVpnyPTRziGkMt0a67uYvjCcV1f45vLb3GzdbC0d6gC1ZPIBaM8Fx0YdAkqSljABC1U5wyn46uVyGyRkpjVIdEg11F+wtJcgMXd1SioISN23qRc2ieLJlUFIU7A11XqtQm1HqYMw35bN0tuZbnWMKTeRR3Pm7pkMdP9iNoPD4lO63ycPvOx3e9acMByuFF9PfJ59Y/NeghLRNFPEU7f1izwdukT+cMuP2Irm/edCfz3vy5NL13BJiaGcZBueTzf4TbJgb+JQ9F23n9ir2iAYqZNKdolDs3cNhesRi9KhoEStiQD4RDPd4tnOCaJQSVTxyDS5IVb4hmZenvpnK8bNK4Z0hSY8c1wDU97Ul9hU3HPQwuQtwSvy36j+Xf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2026 21:17:19.5660 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 893ad6e3-076e-4606-c4d0-08df3b822d06 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000166C1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6235 Hi, This series by Cosmin fixes several mlx5e offload issues. 1. Fix fs root table cleanup bug. 2. Fix IPsec encap serialization bugs. 3. Fix a deadlock between HCA devcom lock and mode_lock. 4. Fix uplink unbind deadlocks by not holding mode_lock across removal. All eswitch operation initiators wait for ongoing ones to finish first. Unblocked by 3. 5. Fix races between profile cleanup/init and IPsec policy/state add. Unblocked by 4. 6+7. Block eswitch mode changes before accessing the IPsec context during policy and SA creation. Unblocked by 5. 8. Serialize TC/IPsec exclusion counters with a per-device spinlock. Unblocked by 6+7. Regards, Tariq V3: - Added several new fixes, all found by internal Sashiko. - Addressed a few Sashiko comments from V2. - Renamed V2 patches 1-2 to "Block E-Switch mode changes during IPsec policy creation" and "... during IPsec state creation". - Dropped V2 patch 4, "net/mlx5e: tc: Tie esw & accel blocking refs to the flow's lifetime", to be submitted separately. - Exclusion counters: use a spinlock instead of a mutex, as some callers run in atomic context. V2: https://lore.kernel.org/netdev/20260930121119.141953-1-tariqt@nvidia.com/ - Use mlx5_esw_lock() in mlx5_eswitch_block_mode() (Sashiko) - Clarified the fix split across first two patches (Sashiko) - More careful dereferencing priv->mdev in mlx5e_xfrm_add_state() (Sashiko) - Avoided spurious error message during IPsec SW fallback (Sashiko) - Harmonized check_users arg for policy & state add (Sashiko) - Clarified the scope of the "tc: tie..." fix (Sashiko) - Moved macsec patches into a separate series. V1: https://lore.kernel.org/netdev/20260917175433.4090878-1-tariqt@nvidia.com/ Cosmin Ratiu (8): net/mlx5e: Release IPsec root table reference on RX setup failure net/mlx5e: Serialize ipsec encap reservations with eswitch operations net/mlx5e: Take HCA devcom lock before esw->mode_lock net/mlx5e: Fix E-Switch races in uplink unbind net/mlx5e: Fix ipsec core device access during profile changes net/mlx5e: Block E-Switch mode changes during IPsec policy creation net/mlx5e: Block E-Switch mode changes during IPsec state creation net/mlx5e: Serialize TC and IPsec offload exclusion counters .../mellanox/mlx5/core/en_accel/ipsec.c | 95 +++++++++++++------ .../mellanox/mlx5/core/en_accel/ipsec.h | 2 +- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 88 ++++++++--------- .../net/ethernet/mellanox/mlx5/core/en_main.c | 4 +- .../net/ethernet/mellanox/mlx5/core/en_tc.c | 18 ++-- .../mellanox/mlx5/core/esw/ipsec_fs.c | 15 ++- .../mellanox/mlx5/core/esw/ipsec_fs.h | 6 ++ .../net/ethernet/mellanox/mlx5/core/eswitch.c | 24 +++++ .../net/ethernet/mellanox/mlx5/core/eswitch.h | 15 ++- .../mellanox/mlx5/core/eswitch_offloads.c | 88 +++++++++-------- .../net/ethernet/mellanox/mlx5/core/main.c | 1 + include/linux/mlx5/driver.h | 8 +- 12 files changed, 231 insertions(+), 133 deletions(-) base-commit: fafbc4051123d5459ea6950899cec08ed946e278 -- 2.44.0