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Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Andrea Parri , Boris Pismenny , Cosmin Ratiu , Dragos Tatulea , "Gal Pressman" , Jeroen Massar , Jianbo Liu , Kuniyuki Iwashima , Leon Romanovsky , open list , , Mark Bloch , "Patrisious Haddad" , Prathamesh Deshpande , Raed Salem , Roi Dayan , Saeed Mahameed , Shay Drory , Simon Horman , Steffen Klassert , Tariq Toukan Subject: [PATCH net V3 2/8] net/mlx5e: Serialize ipsec encap reservations with eswitch operations Date: Thu, 5 Nov 2026 23:16:30 +0200 Message-ID: <20261105211637.1083978-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261105211637.1083978-1-tariqt@nvidia.com> References: <20261105211637.1083978-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF00022BD5:EE_|DS0PR12MB7876:EE_ X-MS-Office365-Filtering-Correlation-Id: f758fa48-602d-4d9b-c668-08df3b82364f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|376014|7416014|23010399003|9063799003|6133799003|22082099003|18002099003|10067099003|56012099006|261021130227099003|261022113327099003|11063799006|261026121527099003|261021123027099003|261021135927099003|261026140227099003|261022105027099003|261028144727099003|261026130827099003|261022115727099003|261021121427099003|261009223027099003|261102123227099003|261022075727099003|261026135527099003|261021133027099003; X-Microsoft-Antispam-Message-Info: 9zW4PlWIZRVmkFjVAkP/CwjpHaFmfUhXh6+be8xhH32zq1UxIpl7aBPTomNoS9uwyqLRefDv+mCmqt5wvGvGjeUYwpvNa4S5NCck8PEicHSN7v3suAbn73Le08FoIqa31mfSuAqBwqQmIith6WNaRjbIswDBOPLxUYWnCqqAjASb6dHzyWFv90rNA3m5pres1eZ+feuF63V/YA/H1G+cdnKhfwJCsO1MIynruPfqAIA5RNPLbGO6siERYN6k5gFGnzZbtto6NREjX84kbQYGpVNRt91pNBdsflZyAlFFgSJ0XfVMVAYnaRrY7F0H07uACNkzt4Qbhy9PVwI6+sYIXtt64wX0BIW491vpv7zku/fV0CGEGRKdFendgzcniG5E1entQtaMyMM3JlgmKjYVeRGcmD+o1fDZ1d0795R/fO6rZGVNZRZB07TrB0/UDXRPq/UQKrC6/UqLB2Uc/7ZQajiiUpUzqb2n2ew6G8Tf5e5d1fDxpGdJSfoNe+gUbVQb+Z8i27xbIokjZUniDPmomnt9ezc34X4246Og0O00dApoHfkPGL+/8Z9XACsxVm8I6iU3wZNQlSfyud+xBOdVkKQoRoJ98l1wFez/0Uz/+cCvGmqG3WJqvfj2PrDnV07nViUT9qp3sqRpQVPAfe10vg5Lxv1NeMIkG/cJteZdPM41Ne1fmex+Jqmf2av2881rzlC8IkGzE4M2SabKswa+Bg== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(376014)(7416014)(23010399003)(9063799003)(6133799003)(22082099003)(18002099003)(10067099003)(56012099006)(261021130227099003)(261022113327099003)(11063799006)(261026121527099003)(261021123027099003)(261021135927099003)(261026140227099003)(261022105027099003)(261028144727099003)(261026130827099003)(261022115727099003)(261021121427099003)(261009223027099003)(261102123227099003)(261022075727099003)(261026135527099003)(261021133027099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ECn+t3htk7TJRlIZqTdEJhowUV6w2kS7rnn+BH+6EyVKsSOu/FywNZSIlSrO90tRo9oWlSAY9jREIUtVXKy2eSFTYpXE32AKzWaKLi9BIXSLddnDCgvIXO62cGt508S0bN3qa7VwNu8wecNwDpYCls/0qO93Ax2dOb1CFMD91dwVZV/zZets5nEi4szLZE3HEyrA0A8gU4JIni1VUXG2julkwGTZmNctFdoIGtExfGq7k6yjIXSUvpr//NIUWbi0dKv6gHOp4Wj4l9MArVn4OwcLLSijZrxZfLjFnlyY2iVJn5Wqz/VPRjtzLSgk/M7Dm95C5sKKiOLAJWZrheQvCElGXD1zIn84/qAA8vG8xBh9CZY+Q3OnUDYXiBXSMW1qEaTFv6KWCCtajSxm+ta6qq+czpP/uIQrXi1PGW8GCsQU44RIcRZu1Cvge8bjF9EH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2026 21:17:35.1079 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f758fa48-602d-4d9b-c668-08df3b82364f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF00022BD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7876 From: Cosmin Ratiu mlx5_eswitch_block_encap() takes mode_lock but ignores eswitch_operation_in_progress. mlx5_devlink_eswitch_encap_mode_set() claims the operation and drops mode_lock while rebuilding the FDB and updating offloads.encap, so a reservation can read a stale or rolled-back encap value. In diagram form: T1: first IPsec SA (NIC table) T2: encap none -> basic mlx5_devlink_eswitch_encap_mode_set() down_write(&esw->mode_lock) sees num_block_encap == 0 eswitch_operation_in_progress = true up_write(&esw->mode_lock) esw_destroy_offloads_fdb_tables() mlx5e_xfrm_add_state() mlx5e_ipsec_fs_tunnel_allowed() mlx5_eswitch_block_encap() down_write(&esw->mode_lock) reads encap == NONE num_block_encap++ up_write(&esw->mode_lock) esw->offloads.encap = BASIC esw_create_offloads_fdb_tables() The race happens therefore because offloads.encap is not consistently accessed under mode_lock. There are other variations of the above race (e.g. in rollback, or in tx_create()). Use mlx5_esw_lock() to reject a reservation while an operation is in progress. This implies changing mlx5e_ipsec_fs_tunnel_allowed() to propagate the error. Note that these are not new failure modes as it seems on first glance, because if the eswitch_operation_in_progress flag is set, rx_get()/tx_get()->mlx5_eswitch_block_mode() already fails with -EBUSY. The new code simply protects against an operation initiated in the short window after mlx5_eswitch_block_mode(). This race was found by Sashiko during inspection of another patch of this series. No attempt has been made to trigger it, as it requires very precise timing. Fixes: baac8351f74c ("net/mlx5e: Reduce eswitch mode_lock protection context") Signed-off-by: Cosmin Ratiu Reviewed-by: Jianbo Liu Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec.c | 5 ++++- .../mellanox/mlx5/core/en_accel/ipsec.h | 2 +- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 21 ++++++++++++------- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 6 +++--- .../mellanox/mlx5/core/eswitch_offloads.c | 20 +++++++++++------- 5 files changed, 35 insertions(+), 19 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 7e991a09b3ff..7bc5d07b4321 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -812,7 +812,10 @@ static int mlx5e_xfrm_add_state(struct net_device *dev, if (x->props.mode == XFRM_MODE_TUNNEL && x->xso.type == XFRM_DEV_OFFLOAD_PACKET) { - allow_tunnel_mode = mlx5e_ipsec_fs_tunnel_allowed(sa_entry); + err = mlx5e_ipsec_fs_tunnel_allowed(sa_entry); + if (err < 0) + goto unblock_mode; + allow_tunnel_mode = err; if (!allow_tunnel_mode) { NL_SET_ERR_MSG_MOD(extack, "Packet offload tunnel mode is disabled due to encap settings"); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h index abcbd38db9db..f4b2d7b950c0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.h @@ -320,7 +320,7 @@ void mlx5e_accel_ipsec_fs_del_rule(struct mlx5e_ipsec_sa_entry *sa_entry); int mlx5e_accel_ipsec_fs_add_pol(struct mlx5e_ipsec_pol_entry *pol_entry); void mlx5e_accel_ipsec_fs_del_pol(struct mlx5e_ipsec_pol_entry *pol_entry); void mlx5e_accel_ipsec_fs_modify(struct mlx5e_ipsec_sa_entry *sa_entry); -bool mlx5e_ipsec_fs_tunnel_allowed(struct mlx5e_ipsec_sa_entry *sa_entry); +int mlx5e_ipsec_fs_tunnel_allowed(struct mlx5e_ipsec_sa_entry *sa_entry); int mlx5_ipsec_create_sa_ctx(struct mlx5e_ipsec_sa_entry *sa_entry); void mlx5_ipsec_free_sa_ctx(struct mlx5e_ipsec_sa_entry *sa_entry); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index fd9fbf359333..1529d4730323 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -1072,9 +1072,12 @@ static int rx_create(struct mlx5_core_dev *mdev, struct mlx5e_ipsec *ipsec, goto err_fs_ft_sa_sel; /* Create FT */ - if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_TUNNEL) - rx->allow_tunnel_mode = - mlx5_eswitch_block_encap(mdev, rx == ipsec->rx_esw); + if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_TUNNEL) { + err = mlx5_eswitch_block_encap(mdev, rx == ipsec->rx_esw); + if (err < 0) + goto err_fs_ft; + rx->allow_tunnel_mode = err; + } if (rx->allow_tunnel_mode) flags = MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; @@ -1315,9 +1318,12 @@ static int tx_create(struct mlx5e_ipsec *ipsec, struct mlx5e_ipsec_tx *tx, if (err) goto err_status_rule; - if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_TUNNEL) - tx->allow_tunnel_mode = - mlx5_eswitch_block_encap(mdev, tx == ipsec->tx_esw); + if (mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_TUNNEL) { + err = mlx5_eswitch_block_encap(mdev, tx == ipsec->tx_esw); + if (err < 0) + goto err_encap; + tx->allow_tunnel_mode = err; + } if (tx->allow_tunnel_mode) flags = MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT; @@ -1387,6 +1393,7 @@ static int tx_create(struct mlx5e_ipsec *ipsec, struct mlx5e_ipsec_tx *tx, err_sa_ft: if (tx->allow_tunnel_mode) mlx5_eswitch_unblock_encap(mdev); +err_encap: mlx5_del_flow_rules(tx->status.rule); err_status_rule: mlx5_destroy_flow_table(tx->ft.status); @@ -2854,7 +2861,7 @@ void mlx5e_accel_ipsec_fs_modify(struct mlx5e_ipsec_sa_entry *sa_entry) memcpy(sa_entry, &sa_entry_shadow, sizeof(*sa_entry)); } -bool mlx5e_ipsec_fs_tunnel_allowed(struct mlx5e_ipsec_sa_entry *sa_entry) +int mlx5e_ipsec_fs_tunnel_allowed(struct mlx5e_ipsec_sa_entry *sa_entry) { struct mlx5e_ipsec *ipsec = sa_entry->ipsec; struct xfrm_state *x = sa_entry->x; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index e9cbcd73b23f..928b20e73d37 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -967,7 +967,7 @@ void mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw); bool mlx5_eswitch_is_peer(struct mlx5_eswitch *esw, struct mlx5_eswitch *peer_esw); -bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb); +int mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb); void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev); int mlx5_eswitch_block_mode(struct mlx5_core_dev *dev); @@ -1071,10 +1071,10 @@ mlx5_eswitch_reload_ib_reps(struct mlx5_eswitch *esw) static inline void mlx5_eswitch_unload_reps(struct mlx5_eswitch *esw) {} -static inline bool +static inline int mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb) { - return true; + return 1; } static inline void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index c712848b202d..7a0131e26ff0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4712,25 +4712,31 @@ int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode) return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode); } -bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb) +/* Return 1 if allowed, 0 if disallowed by the configuration, or -EBUSY + * if an eswitch operation is in progress. + */ +int mlx5_eswitch_block_encap(struct mlx5_core_dev *dev, bool from_fdb) { struct mlx5_eswitch *esw = dev->priv.eswitch; enum devlink_eswitch_encap_mode encap; - bool allow_tunnel = false; + int ret; if (!mlx5_esw_allowed(esw)) - return true; + return 1; + + ret = mlx5_esw_lock(esw); + if (ret) + return ret; - down_write(&esw->mode_lock); encap = esw->offloads.encap; if (esw->mode == MLX5_ESWITCH_LEGACY || (encap == DEVLINK_ESWITCH_ENCAP_MODE_NONE && !from_fdb)) { - allow_tunnel = true; + ret = 1; esw->offloads.num_block_encap++; } - up_write(&esw->mode_lock); + mlx5_esw_unlock(esw); - return allow_tunnel; + return ret; } void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev) -- 2.44.0