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Thu, 05 Nov 2026 15:14:22 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cdb70a73c99sm14382a12.20.2026.11.05.15.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 15:14:20 -0800 (PST) From: Rosen Penev To: netdev@vger.kernel.org Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jeff Garzik , David Gibson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH net] net: ibm: emac: fix MR0 write in emac_rx_enable() Date: Thu, 5 Nov 2026 15:14:17 -0800 Message-ID: <20261105231417.119930-1-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When an asynchronous RX disable is still in progress, emac_rx_enable() waits for MR0[RXI] with while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) which assigns only the RXI bit to r, as & binds tighter than =. The following write of r | EMAC_MR0_RXE then clears every other MR0 bit, including TXE, and TX stays stopped until the watchdog resets the EMAC. This path is taken when RX is restarted after an RX descriptor error. Tested on a Cisco Meraki MX60. Fixes: 1d3bb996481e ("Device tree aware EMAC driver") Signed-off-by: Rosen Penev --- drivers/net/ethernet/ibm/emac/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/ibm/emac/core.c b/drivers/net/ethernet/ibm/emac/core.c index 640618c0a09e..b676b286e339 100644 --- a/drivers/net/ethernet/ibm/emac/core.c +++ b/drivers/net/ethernet/ibm/emac/core.c @@ -249,7 +249,7 @@ static void emac_rx_enable(struct emac_instance *dev) if (unlikely(!(r & EMAC_MR0_RXI))) { /* Wait if previous async disable is still in progress */ int n = dev->stop_timeout; - while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n) { + while (!((r = in_be32(&p->mr0)) & EMAC_MR0_RXI) && n) { udelay(1); --n; } -- 2.56.0