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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b25e4a63f6sm389041c88.9.2026.11.05.15.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 15:51:39 -0800 (PST) From: Anusha Arun Nandi To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Manivannan Sadhasivam , Bryan O'Donoghue Cc: gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: phy: qcom: Add common qcom,csi2-phy Date: Thu, 5 Nov 2026 15:51:34 -0800 Message-Id: <20261105235137.2635442-2-anusha.nandi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261105235137.2635442-1-anusha.nandi@oss.qualcomm.com> References: <20261105235137.2635442-1-anusha.nandi@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDA5NSBTYWx0ZWRfX2lBY4WRGKkG/ gvjwWRwI6L4onmnHBWGBJ9i+qaJ1+L6rB38nVdpXAPvPpNuQq+aqFXkoOf8SXDS5d0y8SZBynn3 X19/BKG1Xk9Tp9Y5gcHkX3J9WTf+rE40vdfiThx90d5XGANzVAOrNebyZm+HYTBRxEe8NIhuFpc Uszcwar1Uum3hdvPTtOUE2O7DGz/B9PXs6Wu/1RyyXOKGj26nmfwziOGW7SpcPsM2TcaaYS2ivt JsCzrFMk6bzd76otxQcE03skN5Kcv4hIDEdeyqpFmgU0YsdDi7U1YjqbJizmST/r7nAQaWxzgtW PXzNU898JtE3Bes/8E6iQ0lZlhcnL7CgKzHLYLCA5jlZYHeKPmm7kDsQGXAnW3vzeVDpAAaZNCQ osIKFb0zTwuCyNzm1J8M2h/5Dw84sHLPulZNXn0rQbPv+LsCTDP0g7HMS3YXhBQPrqdrlhaXcnz RhIcmPdJgOo4tQzDagQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDA5NSBTYWx0ZWRfX4htZxA7omU+I aD8EJLXE1SgmFZqjwzKXrnoNrbsO188KBz6+rADqHrZTZ9p3FAMkoE+7IM9L26vcUBDeL6qwF09 8m+/8Tu+qDpvlaWFMMUwlVL9TzJ049k= X-Proofpoint-GUID: k8OgZOSLVmjeps6-vP68GyUYuYaqGi0N X-Authority-Analysis: v=2.4 cv=P4ivFSAu c=1 sm=1 tr=0 ts=6aed168d cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=Qi6pjpdL7GA_D8ehSiUA:9 a=vr4QvYf-bLy2KjpDp97w:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: k8OgZOSLVmjeps6-vP68GyUYuYaqGi0N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_06,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 spamscore=0 phishscore=0 suspectscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611050095 SA8775P, QCS8300 and SC7280 CSI2 PHYs are bit-for-bit identical in devicetree shape (ports, bus-type, data-lanes, operating-points-v2, clocks, single "top" power-domain, vdda-hs/vdda-lp supplies). Describe all three with a single qcom,csi2-phy.yaml and a compatible oneOf, rather than one standalone schema per SoC. QCS8300 is further required to be paired with a qcom,sa8775p-csi2-phy fallback compatible, the same way other Qualcomm bindings express full hardware compatibility between two SoCs (see qcom,qusb2-phy.yaml); this lets the driver bind QCS8300 nodes via its qcom,sa8775p-csi2-phy match entry rather than carrying a duplicate one. qcom,x1e80100-csi2-phy.yaml is a separate PHY with a different shape (3 clocks, 3 power-domains, different supply names, DPHY split-mode support) and is left untouched, but port@0's DPHY split-mode definition (two endpoints, lane-count constraint) is cloned into this schema rather than dropped, since this PHY supports the same split mode. The supply names are vdda-hs/vdda-lp rather than the hardware's own power-rail names, since those names aren't guaranteed to stay consistent across future platforms using this binding. Reviewed-by: Jigarkumar Zala Signed-off-by: Anusha Arun Nandi --- .../bindings/phy/qcom,csi2-phy.yaml | 201 ++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml new file mode 100644 index 000000000000..44791802a3ed --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,csi2-phy.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,csi2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CSI2 PHY + +maintainers: + - Anusha Arun Nandi + +description: + Qualcomm MIPI CSI2 D-PHY. Connects MIPI CSI2 sensors to Qualcomm's Camera + CSI Decoder. + +properties: + compatible: + oneOf: + - enum: + - qcom,sa8775p-csi2-phy + - qcom,sc7280-csi2-phy + - items: + - enum: + - qcom,qcs8300-csi2-phy + - const: qcom,sa8775p-csi2-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: core + - const: timer + + interrupts: + maxItems: 1 + + operating-points-v2: true + + opp-table: + type: object + + power-domains: + items: + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: top + + vdda-hs-supply: + description: Phandle to PHY supply. + + vdda-lp-supply: + description: Phandle to PLL supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: + Sensor input. Always present. A single sensor is described by a + single endpoint with one to four data lanes, numbered 1-4. The + clock lane is position 0. + + DPHY split mode, where two independent sensors share the PHY, is + described by two endpoints. endpoint@0 uses data lanes 1 or 1-2, + clock lane position 0; endpoint@1 uses data lane 3, clock lane + position 4. + + unevaluatedProperties: false + + patternProperties: + "^endpoint(@[01])?$": + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + default: 4 + + data-lanes: + minItems: 1 + maxItems: 4 + items: + minimum: 1 + maximum: 4 + description: + Data lane positions following this endpoint's clock + lane. Positions are a per-port logical numbering, not + package pad or ball positions. + + required: + - data-lanes + - remote-endpoint + + allOf: + - if: + required: + - endpoint@1 + then: + properties: + endpoint@0: + properties: + data-lanes: + maxItems: 2 + items: + maximum: 2 + endpoint@1: + properties: + data-lanes: + items: + - const: 3 + required: + - endpoint@0 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output to the CAMSS CSID controller. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - operating-points-v2 + - power-domains + - power-domain-names + - vdda-hs-supply + - vdda-lp-supply + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + + phy@ac9c000 { + compatible = "qcom,sa8775p-csi2-phy"; + reg = <0x0ac9c000 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "core", + "timer"; + + interrupts = ; + + operating-points-v2 = <&csiphy_opp_table>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + vdda-hs-supply = <&vreg_l4a>; + vdda-lp-supply = <&vreg_l1c>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + csiphy0_in: endpoint { + bus-type = ; + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_out>; + }; + }; + + port@1 { + reg = <1>; + csiphy0_out: endpoint { + remote-endpoint = <&csid_in>; + }; + }; + }; + + csiphy_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + }; -- 2.34.1