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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b25e4a63f6sm389041c88.9.2026.11.05.15.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 15:51:40 -0800 (PST) From: Anusha Arun Nandi To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Manivannan Sadhasivam , Bryan O'Donoghue Cc: gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/4] phy: qcom-mipi-csi2: Make OPP table optional Date: Thu, 5 Nov 2026 15:51:35 -0800 Message-Id: <20261105235137.2635442-3-anusha.nandi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261105235137.2635442-1-anusha.nandi@oss.qualcomm.com> References: <20261105235137.2635442-1-anusha.nandi@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDA5NSBTYWx0ZWRfX5xOeMILKlBFZ SN0YB32lzBVLHR2hLUySzYy9UZ5W9Hqgb6fKNEFxpsP7ZzsH85VIi5veJrrqWGZ1TlFbQp9ynqw 0q7tFLokeHkzXRpznBw/zkWav/ejJcg= X-Proofpoint-GUID: drEfCLS4OGXy1eA7Z6NigzDV2eklmzVT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDA5NSBTYWx0ZWRfX1ELexHI6irXK 2xcJGbKdaxpqB4jxOBeOgqPLP+GNKCjs+Vx68apCp7C7zGiowSrmOAUR0Y41zE4Scu39GnSd09G 4p+aGBPpElNUZ3eO1PeR5tB2oUYmKoZFX3eCH9437rXKDDj3ALCjrVFUfCe+A/fK9bwNuZrcnzz zWwjJO6f0jUowbBcRq2xbJ6VSm8ZKsQeurqW0PDVvxGUghltOIJxGrvChvHj+0mhjJqOaT3Uy12 kLN0dlg64QDFznHpVMOaBvEu9T1d9cPvH0rilen6qRGMQyao0PNT2P1zfUHE6CcT/L6k8rFgl7v TLlVsG/gBQDuU70ATkEXENnL6LqKeGpJk6MeX0YFsUBdHmyljYU1/VmEzoUXmBqoBlQnS19yTvK kU6eFt/DaRCWjIdt9wcMBSwzpGR8tOvTZK7slr4YsRVDuPzHQfPwtQEJHSFfB6G5568cyP4/HoE H6G3ccgWYAgpGFKeyrA== X-Proofpoint-ORIG-GUID: drEfCLS4OGXy1eA7Z6NigzDV2eklmzVT X-Authority-Analysis: v=2.4 cv=ZIZCCn7b c=1 sm=1 tr=0 ts=6aed168e cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=xhLwaI6HiHkcQTGlYsAA:9 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_06,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611050095 Not every SoC the generic MIPI CSI2 PHY driver supports needs an OPP table: a CSIPHY with only a single, unscaled power-domain has no performance state to vote on, so running its "core" clock through the OPP framework buys nothing over a plain clk_set_rate(). Add a no_opp flag to struct mipi_csi2phy_soc_cfg and skip devm_pm_opp_set_clkname()/devm_pm_opp_of_add_table() in probe() and the OPP/performance-state handling in phy_qcom_mipi_csi2_set_clock_rates() when it's set, falling back to clk_round_rate()/clk_set_rate() on the timer clock only. x1e80100 doesn't set no_opp, so this is a no-op for it. The "core"/ "timer" clock-name strings themselves stay hardcoded literals: every SoC this driver supports uses the same two names, so there's nothing to make configurable there. Reviewed-by: Jigarkumar Zala Signed-off-by: Anusha Arun Nandi --- .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 72 ++++++++++--------- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 3 + 2 files changed, 42 insertions(+), 33 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c index 269232499fca..8bebc943a771 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -32,40 +32,43 @@ phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy, unsigned long opp_rate = link_freq / 4; struct dev_pm_opp *opp; long timer_rate; - int i, pstate; + int i = 0, pstate; int ret; - opp = dev_pm_opp_find_freq_ceil(dev, &opp_rate); - if (IS_ERR(opp)) { - dev_err(csi2phy->dev, "Couldn't find ceiling for %lld Hz\n", - link_freq); - return PTR_ERR(opp); - } + if (!csi2phy->soc_cfg->no_opp) { + opp = dev_pm_opp_find_freq_ceil(dev, &opp_rate); + if (IS_ERR(opp)) { + dev_err(csi2phy->dev, "Couldn't find ceiling for %lld Hz\n", + link_freq); + return PTR_ERR(opp); + } - pstate = 0; - for (i = 0; csi2phy->pd_list && i < csi2phy->pd_list->num_pds; i++) { - unsigned int perf; + pstate = 0; + for (i = 0; csi2phy->pd_list && i < csi2phy->pd_list->num_pds; i++) { + unsigned int perf; - if (!csi2phy->soc_cfg->genpds[i].scaled) - continue; + if (!csi2phy->soc_cfg->genpds[i].scaled) + continue; - perf = dev_pm_opp_get_required_pstate(opp, pstate); - pstate += 1; + perf = dev_pm_opp_get_required_pstate(opp, pstate); + pstate += 1; - ret = dev_pm_genpd_set_performance_state(csi2phy->pd_list->pd_devs[i], perf); - if (ret) { - dev_err(csi2phy->dev, "Couldn't set perf state %u\n", - perf); - dev_pm_opp_put(opp); - goto unset_pstate; + ret = dev_pm_genpd_set_performance_state(csi2phy->pd_list->pd_devs[i], + perf); + if (ret) { + dev_err(csi2phy->dev, "Couldn't set perf state %u\n", + perf); + dev_pm_opp_put(opp); + goto unset_pstate; + } } - } - dev_pm_opp_put(opp); + dev_pm_opp_put(opp); - ret = dev_pm_opp_set_rate(dev, opp_rate); - if (ret) { - dev_err(csi2phy->dev, "dev_pm_opp_set_rate() fail\n"); - goto unset_opp_rate; + ret = dev_pm_opp_set_rate(dev, opp_rate); + if (ret) { + dev_err(csi2phy->dev, "dev_pm_opp_set_rate() fail\n"); + goto unset_opp_rate; + } } timer_rate = clk_round_rate(csi2phy->timer_clk, link_freq / 4); @@ -83,7 +86,8 @@ phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy, return 0; unset_opp_rate: - dev_pm_opp_set_rate(dev, 0); + if (!csi2phy->soc_cfg->no_opp) + dev_pm_opp_set_rate(dev, 0); unset_pstate: while (i--) { @@ -405,13 +409,15 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) if (!csi2phy->timer_clk) return dev_err_probe(dev, -ENODEV, "no timer clock\n"); - ret = devm_pm_opp_set_clkname(dev, "core"); - if (ret) - return dev_err_probe(dev, ret, "Failed to set opp clkname\n"); + if (!csi2phy->soc_cfg->no_opp) { + ret = devm_pm_opp_set_clkname(dev, "core"); + if (ret) + return dev_err_probe(dev, ret, "Failed to set opp clkname\n"); - ret = devm_pm_opp_of_add_table(dev); - if (ret) - return dev_err_probe(dev, ret, "invalid OPP table in device tree\n"); + ret = devm_pm_opp_of_add_table(dev); + if (ret) + return dev_err_probe(dev, ret, "invalid OPP table in device tree\n"); + } num_supplies = csi2phy->soc_cfg->num_supplies; csi2phy->supplies = devm_kzalloc(dev, sizeof(*csi2phy->supplies) * num_supplies, diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h index 7e55ae007370..6cf9e5b956f7 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -68,6 +68,9 @@ struct mipi_csi2phy_soc_cfg { const char ** const clk_names; const unsigned int num_clk; + /* Skip OPP-based clock/pstate scaling. */ + const bool no_opp; + const struct mipi_csi2_genpd *genpds; const unsigned int num_genpds; }; -- 2.34.1