From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=205.220.168.131 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793922706; b=MAnjlMljMo5lGwNxxNgwL2wJ1pOAYuXjWJMsZ8B84FjY5d/kNN8wlv/2eccDcvxqqmOb Fkublebt3Q3s8dzeMwB+9r8fFhAhmuTmefxo0QLyExbInwbM+rQkivEwSNWKLIa+Rwatq J7Bb1qjo9ERabNbK98H0034KUQyFJf/cpQ4L62+PPSNgy8S6ZVGF/Ixj+ZKZs1uHYzakz 4wsO50clsKXv+fA7e9H+QP33WRfZ6WgcGO68lNHXJYbfPevv/ICvjahj/nTmAZ6yRc8AX hA12jZZMMKGUU4BnKOViCQNZ7n9Agu/B2gR60Zbk+DV4ed8YR2DxQkLzPy7IJVs36Sw== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793922706; h=DMARC-Filter:Received:DKIM-Signature:Received:Received: DKIM-Signature:X-Google-DKIM-Signature:X-Forwarded-Encrypted: X-Gm-Message-State:X-Gm-Gg:X-Received:X-Received:Received:From:To:Cc: Subject:Date:Message-Id:X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding:X-Proofpoint-Spam-Info:X-Proofpoint-GUID: X-Proofpoint-Spam-Details-Enc:X-Proofpoint-ORIG-GUID: X-Authority-Analysis:X-Proofpoint-Virus-Version: X-Proofpoint-Spam-Details; bh=X0kFzvyq0Q1jnZcbpuAo3OSL5P0T77jCze1tSTQGuMc=; b=n0ILcZFuIAnK/WBcTAMDk9EHm5SS5IkCywm0o/9ixkuDLNbIV9gJopPWaoyjXSo7F/SQ tX2qY+ldbIPv+208G1qsyBTAwfpLjHHt4Clxva72TKCMGkqzmQJfJ88GuUsq/uWGCtGwz JUMD1c39iqnqLaWi8gmcoCd7sYPs8skaApxCrPSZmQWHWjgDJFuYrUsbTl59gjDZ4h12C V1MlA7RMtASQoKPsi0wKd6D7rV8O7ng3ROCleV+kJMdlt5Rt5bat9YQJO0B9/652AR5h/ LB3W2FhRZzMk4JgwqxceojkRMCG4kFGOguwjAVlboo2UuYjAy71k4Mq3hni4h62YGZg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=WtGBtEuE; dkim=pass header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=TNCME8Er; arc=none smtp.remote-ip=205.220.168.131 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14147606EE84 for ; Thu, 5 Nov 2026 23:51:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 14147606EE84 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=WtGBtEuE; dkim=pass (2048-bit key, unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=TNCME8Er Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6A5NeP2p3215973 for ; Thu, 5 Nov 2026 23:51:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=X0kFzvyq0Q1 jnZcbpuAo3OSL5P0T77jCze1tSTQGuMc=; b=WtGBtEuEzw8Sp8weC1m4TEthcUa g6MA3/WjTefSJuukhGCNh+0jw9k9GhWDXdwvUUWdOjVnAhphBqgpO+2BBCJOV2wn rdVUNJZ0KPVioVTIXofDAO5j5scZYKSRUujkMwLDrB/8Q4OU5uWZ7RfPdafK5Ck3 spma7bdqTcafDhU7R+fqxCRh3lPnBOE0vsio/EQNeYTVs70GlWJk/0TdvM6sExP/ z6JcLvTkHApihqaPaEzzunfpd5W0nrt1A0LiXvW7JHIzweObjOVWPn0BLiMMfIzs LdwXI114bcXhogemi88MqIFb2SGp+lg0WpOTNO9l8ao/8Xc/1wJsBevkgfA== Received: from mail-dl1-f71.google.com (mail-dl1-f71.google.com [74.125.82.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hs3p9r143-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 05 Nov 2026 23:51:45 +0000 (GMT) Received: by mail-dl1-f71.google.com with SMTP id a92af1059eb24-1a5005fd0f8so125872c88.0 for ; Thu, 05 Nov 2026 15:51:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1793922704; x=1794527504; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=X0kFzvyq0Q1jnZcbpuAo3OSL5P0T77jCze1tSTQGuMc=; b=TNCME8Erumqmudda8b8boCKXL1SPKAXO+CH6ch8/7PDZc0ewGeOQh+B0yuzQNCnU9T W92LCnWcTG7xyCJdTNY3oD1eO1voK4/h+iLEupgFmk0QCd/AzsxO+3yUuXaoNmQVHR9g Isxt+5itAe4lva1JaPbMq9T3JWgNDqbBR8X6iFPcq+0Usu9qN/oQFyS4XTNoQYFqdskN HZHUY00fTXXNoyEO7yaDp0nQwh7H/OQXRmpEzBGrDRQinSXtTEghxU/P9+itjO256fZA WNwNYGRGMVkRrnq4F9s/ZrB2bilehM2ogHrkPUsKbthAqSlaywdiZObK967/oGuxViz3 PWNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1793922704; x=1794527504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=X0kFzvyq0Q1jnZcbpuAo3OSL5P0T77jCze1tSTQGuMc=; b=edtLHFm1doU+2p8llADygZgaP7adDP6fT9DoqehqaWpINiPq7VRtv0xTAjbkh5+LBY XZIjOk/WhyfNNZ5SwbSYWZeYiq4pJ3GJhZaRBZyUJUgn4w7sI00KI1dGAhLGCNfGrQ2d dhpKp2q2w1L4fvNI3GPB8Veol95/GgqAT/tTl3exXhLOrd6iQHEqqGOvjv/A66SzIR5p fy79kFMWNirlyQSRKFNdlibKiU+m3dM76CGNeJmT/6Nk9/BWL78NXCBGKQ+BWe/xx2EQ SsB3l7ySJKg1DZvtgJUmxR9boU9+kD0hoNIZVn5UXUwgVk70cDmiyhL1s+2H/2PrrK24 oDgw== X-Forwarded-Encrypted: i=1; AKwUvBzxLkJ4u7RUmY+/6xAWJKucB4WePczd4rp/oZwnzbU3TcB5SJ+lz7xGKu8WBGeRMj4paIf47gLMF24fooQ=@vger.kernel.org X-Gm-Message-State: APuU4Z/18jzpGMq4VbLAalPJDJdAZ2cpHO6GuFhRb+pilgWRhtYJv0Nf a1lYYtUfSA5/zl3yojdaoKbtH5F4dEC/x+A9Cgoo6pm07Xk7pRO/d9RhOPwGwcuVhZ2SH80TSWh Wn+oE+o0D67jyBBOP14k0WPal6JuugW7dmEh6ONw1Up+OIl0rb6j9lHuhkxrPJ3jH2xA= X-Gm-Gg: AYBFou3EElLEoZj4pC5fprwzqJ3x8ecB2J2XUKA9D2ZU4O5vgaeAdEInFl3tGuApyVb zt+upIZ9rm2dDhc4nV82CAIQgR4B/e5Ft6bNpzcg4ghJ6W2MpQ5921xli5AUBnqS8swI+t8fzpe e+7QxuBJ5ZxbqzNLAQYeDWyBXvVpk35HEpJiBrdMsPAuBwyE+QcmpfJU8qC3V0FwhhGQbC9lq51 J8c+GzBkdLa4xCDSApvOkOTpIPLP2LpUrrBQAk9YEjOh4RayCB5cyLcla7RQx4lP3RhMVTJihH3 XVdkwj7abtO/U80dOwN8lSxeCDoN8gATTN9RAo6odupV9E2tBa2cHcbc0hS7D8P8YDDsfAyuYCh Tw3MMc0SFa+e/8j9TTNi72C3E1R86Z9wWVOdkkrdxw47A5MS5uQq9h2Dmdhu6HO9HwYJiLkoR4G KIpTaDZzuhDJu0TH8AFL9DopdoawI= X-Received: by 2002:a05:701a:ca03:b0:14f:505d:813 with SMTP id a92af1059eb24-1b25d37e2e1mr742545c88.41.1793922704137; Thu, 05 Nov 2026 15:51:44 -0800 (PST) X-Received: by 2002:a05:701a:ca03:b0:14f:505d:813 with SMTP id a92af1059eb24-1b25d37e2e1mr742490c88.41.1793922703457; Thu, 05 Nov 2026 15:51:43 -0800 (PST) Received: from hu-aarunnan-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b25e4a63f6sm389041c88.9.2026.11.05.15.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2026 15:51:43 -0800 (PST) From: Anusha Arun Nandi To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Manivannan Sadhasivam , Bryan O'Donoghue Cc: gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/4] phy: qcom-mipi-csi2: Add sc7280 D-PHY provider Date: Thu, 5 Nov 2026 15:51:37 -0800 Message-Id: <20261105235137.2635442-5-anusha.nandi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261105235137.2635442-1-anusha.nandi@oss.qualcomm.com> References: <20261105235137.2635442-1-anusha.nandi@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA1MDA5NSBTYWx0ZWRfX63R5QDpRBRSC h9NRes274TefGtch4b2aX/trURkkqT5WpNzyoWNOMy1isBnqfgaLdR3K6eM8VR/ipmh+SiAElwN skeFB1zMtcW6Y/GPcPTjkG+PO86+b+o= X-Proofpoint-GUID: duyCuDDLkfs6sjRJIJei4sq6XEzOyHrt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA1MDA5NSBTYWx0ZWRfX8ipN8mOTegMU LzQwX3Alj6IwxYdk2aT/LadtFWN8b1HcfV2Uw4GVhYAV3NuDDTlRwFI1OF5Jnn2ulxSemU/bmtd tuDT3SmzraQanRb0qsGIQOlHNSBreSpj61aMPaVfSoZLJNOss/xdB5I168rXcqNco4R/O9ygt9g JMpQlHm6TqEaiOmcopUkTVJEVq7jUkI6/C14hrRiAvtTVZ63wzzRvn6t6K8D+rEJDjJ36dWjbCA S9HUzAsFKAOeChvecNw8z2levVGfBnlFbz/9Ujs4DRcazL+V5ZMX3qYTMjiBXR+jFedqf9hQGlY aYAjaL1/vn/Cc6RqmTQIoz5Eql5C0T7wJd3N/jtHwjSZ3G728Yutgfiz4EW/0NP1ERPcohBZ9Fw oYieaserGA8V3kB90FVm6Kf/HLypVUqAthjzpjIPR7MqMMmEN9LLXtu0HrOdrsAMWb+UZ+qdJDm A8W9wYHZ3u7taPwSGZw== X-Proofpoint-ORIG-GUID: duyCuDDLkfs6sjRJIJei4sq6XEzOyHrt X-Authority-Analysis: v=2.4 cv=ZIZCCn7b c=1 sm=1 tr=0 ts=6aed1691 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=NbtrdQoedUgDOuZm1b4A:9 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-05_06,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611050095 Add the SC7280 CSIPHY to the generic MIPI CSI2 PHY driver, bound to a new "qcom,sc7280-csi2-phy" compatible and reusing the existing D-PHY 2-phase hw ops (phy_qcom_mipi_csi2_ops_3ph_1_0). The lane_regs_sc7280[] init sequence is the CSIPHY 5nm 2-phase 2.5Gbps 4-lane D-PHY register set ported from the legacy in-tree camss-csiphy-3ph-1-0.c table, with the entries that table left as do-not-program placeholders simply omitted here rather than carried as a new marker. The soc_cfg declares the core/timer clocks (matching x1e80100's and sa8775p's clock-names convention for this pair, both hardcoded literals in the driver) and the vdda-hs/vdda-lp supplies. Like x1e80100 and SA8775P, SC7280's CSIPHY core clock is OPP-scaled against the sensor's link frequency via the shared csiphy_opp_table in kodiak.dtsi, so no_opp is left unset here too. SC7280's CSIPHY has a single power-domain, the Titan Top GDSC, matching camss.c's sc7280_resources.pd_name = "top" and kodiak.dtsi's existing camss node; it is not OPP-scaled, only kept enabled. Reviewed-by: Jigarkumar Zala Signed-off-by: Anusha Arun Nandi --- .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 120 ++++++++++++++++++ .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 + drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 3 files changed, 122 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 52994cb721ec..ad6095b77417 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -489,3 +489,123 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p = { .genpds = sa8775p_genpds, .num_genpds = ARRAY_SIZE(sa8775p_genpds), }; + +/* sc7280 5nm 2PH 2p5Gbps 4 lane DPHY mode */ +static const struct mipi_csi2phy_lane_regs lane_regs_sc7280[] = { + {.reg_addr = 0x0030, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0900, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0908, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0904, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0904, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0004, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x002C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0034, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0010, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x001C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x003C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0008, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0000, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0038, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0014, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0730, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C80, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C88, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C84, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C84, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0704, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x072C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0734, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0710, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x071C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x073C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0708, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0700, .reg_data = 0x80, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x070c, .reg_data = 0xA5, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0738, .reg_data = 0x1F, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0714, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0728, .reg_data = 0x04, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0230, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A00, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A08, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A04, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0A04, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0204, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x022C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0234, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0210, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x021C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x023C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0208, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0200, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0238, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0214, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0430, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B00, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B08, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B04, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0B04, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0404, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x042C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0434, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0410, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x041C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x043C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0408, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0400, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0438, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0414, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0630, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C00, .reg_data = 0x05, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C08, .reg_data = 0x10, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C04, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0C04, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0604, .reg_data = 0x0C, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x062C, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0634, .reg_data = 0x07, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0610, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x061C, .reg_data = 0x08, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x063C, .reg_data = 0xB8, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0608, .reg_data = 0x10, .param_type = CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {.reg_addr = 0x0600, .reg_data = 0x8D, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0638, .reg_data = 0xFE, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0614, .reg_data = 0x60, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0800, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS}, + {.reg_addr = 0x0884, .reg_data = 0x01, .param_type = CSIPHY_DEFAULT_PARAMS}, +}; + +static const char * const sc7280_clks[] = { + "core", + "timer", +}; + +static const char * const sc7280_supplies[] = { + "vdda-hs", + "vdda-lp", +}; + +static const struct mipi_csi2_genpd sc7280_genpds[] = { + { .name = "top", .scaled = false }, +}; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sc7280 = { + .ops = &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info = { + .init_seq = lane_regs_sc7280, + .lane_array_size = ARRAY_SIZE(lane_regs_sc7280), + .common_regs_offset = 0x800, + }, + .supply_names = (const char **)sc7280_supplies, + .num_supplies = ARRAY_SIZE(sc7280_supplies), + .clk_names = (const char **)sc7280_clks, + .num_clk = ARRAY_SIZE(sc7280_clks), + .genpds = sc7280_genpds, + .num_genpds = ARRAY_SIZE(sc7280_genpds), +}; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c index d0e08d4bbea5..a1c3491a43f6 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -455,6 +455,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev) static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] = { { .compatible = "qcom,sa8775p-csi2-phy", .data = &mipi_csi2_dphy_sa8775p }, + { .compatible = "qcom,sc7280-csi2-phy", .data = &mipi_csi2_dphy_sc7280 }, { .compatible = "qcom,x1e80100-csi2-phy", .data = &mipi_csi2_dphy_4nm_x1e }, { } }; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h index f092366a0436..7f25dec7a4e5 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -97,5 +97,6 @@ struct mipi_csi2phy_device { extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sa8775p; +extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_sc7280; #endif /* __PHY_QCOM_MIPI_CSI2_H__ */ -- 2.34.1