From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=205.220.180.131 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793968448; b=SqFBOZnI4MR+OD2tjvIcvAFMMblxS0DUgtXETVtn5ika4yfVfvt8+CENyZwoPVcxyWwJ yXK+ulFWPsphgVfa+Zv/s/fijlrU7T+DnDwJgNjPhctkrRiB5bbOv8SRqMF4yoz5tH4Ie lWUQP7q3RFJ+PO4hasAoaaLhEiXmtMNalTsVgkl01gpFOJdXyGh3FPq+rbyHPOBAV0njT TOy/C0t1MTYxZk0huhWf1cITgK3wE1tTlAG+CnSESbAYLMG2W3KyNdDg6vfXZz35bZxf3 uLE9bh62v6t7aB+yU5I0OkjHJUu/f+bWr+Jn3/8TCIb4I67X6uZbs0k5LxmndssrXqA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793968448; h=DMARC-Filter:Received:DKIM-Signature:Received:Received: DKIM-Signature:X-Google-DKIM-Signature:X-Forwarded-Encrypted: X-Gm-Message-State:X-Gm-Gg:X-Received:X-Received:Received:From:Date: Subject:MIME-Version:Content-Type:Content-Transfer-Encoding: Message-Id:References:In-Reply-To:To:Cc:X-Mailer: X-Developer-Signature:X-Developer-Key:X-Proofpoint-Spam-Details-Enc: X-Proofpoint-Spam-Info:X-Proofpoint-ORIG-GUID:X-Authority-Analysis: X-Proofpoint-GUID:X-Proofpoint-Virus-Version: X-Proofpoint-Spam-Details; bh=nMtphcE2ywtPkQs9Srh3I4+ue2tS5BaAXlhTEBAmapQ=; b=Y0O4nkvcmqXeiv1m2qEVEX4zE297bTPtpS1yq/OuM4Zog0BPPPzJ7UZ/9UQkm432lSjp STiop5FZx6qYiStKbG/QHZEc4a50pmHtXR+Gis0Xwbk1vXP9X+5xwIsojru0xNHhRGGp0 JyP9o3IGLVgHshuKgOtmxD2mV91iye87jfMq8eVYXhbEB43M19HI7Kv5V0fTGiLK8hX+B PL1Mmw/Y8cb/4jSZU//6YNSx1B4SelVHoMr/wb5PXgpMwGHOSCxO/6IxCg87ofdJAFLm4 4SUIgIqv6z4QqHQtpCwPwEhnF7DF6O70DvLMyC1YLWpETiFIg2wMmAy/PNqDc/zDLmg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=S2s4xuVK; dkim=pass header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=IapQ+8Al; arc=none smtp.remote-ip=205.220.180.131 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4343D606D801 for ; Fri, 6 Nov 2026 12:34:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 4343D606D801 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=S2s4xuVK; dkim=pass (2048-bit key, unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=IapQ+8Al Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6A6AP8x73703892 for ; Fri, 6 Nov 2026 12:34:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nMtphcE2ywtPkQs9Srh3I4+ue2tS5BaAXlhTEBAmapQ=; b=S2s4xuVKlVeN5BcR VB+PMCP0Qcqife2lTjvIcbRvfW2LtTml41/8U5uO5Qm8ZUnQ3K05i0lWznSJcUF6 d2ZMMMSXb2+0vIMU8lFYmUumnNlAJZDBWm40nx5CpVk9f7I4jfNbhAT3bHjGBI3r hFlmZqvzlh5Iy+rHnx/e8im/gorBnsv6DoYUedcEowuzF6CH6AgRRPfJAp3SZqHt QFNGyalIl1S5CAnHdEnWQvAtfffctOSfScPtV4GijdVpss45/zpdGB1YFJzDx47e xpFjfwKmnKNZgpHj/vuSgVMv+kH1+lJXHGpwglepAQCG6bsodqozIqiH7PaedIzC YCdIDw== Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hs3pa2ttb-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 06 Nov 2026 12:34:06 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-36f1e7d9d4dso1297499eec.0 for ; Fri, 06 Nov 2026 04:34:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1793968445; x=1794573245; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=nMtphcE2ywtPkQs9Srh3I4+ue2tS5BaAXlhTEBAmapQ=; b=IapQ+8AltmDkRQvvO28FSgKzxQ9eEACHYJUP/xYMNTv+fdPxHG8nRN38MSb7DyfyPL QmMTljAw7sBvYyl1uWWdOnLZ8Dr8c0K2FnIs1jcCsOKgAJlC9BqWVZ/X+gZVJhuKQUvQ e2YJERezeZRzwhcVPj6gBAZ4OK3GcIgdHjjv6Vh2sw7auWbhvjq3OyTzOgO4BD+TPXRw gO/cimgAKaxz9vVxvgdpScuWBVKyfgWfBnVCLmZA+QXIVXvPxKMZBvan1WlrayIvsqqE qBMKQ/Ix1RmRE30DcFFNdE1Ji6gTxbd93rbl+eABUOAI/n5njRxuj/wj5AeiyBpZ+b6K 4Saw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1793968445; x=1794573245; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=nMtphcE2ywtPkQs9Srh3I4+ue2tS5BaAXlhTEBAmapQ=; b=GyfBAM1669RXCp3dGD1KReoQEEObY05EV7DCEgvtBibiqgA3moY5njJodS1NXCAv4N qbd47tscUbxhQ8W2/z1dqOSVQHZ6jHoKeAPhp/4cAJ+l3TkI+nB2motBjrNBvIGP74Q8 zY777HTRq48fqh/Koz3qHUJbkund3pwXEkXB3BTJ0GVTTusP5LFfL5zxxlvyrjxxlifQ +KRV4M/y+pTHvbkG62knrZrnTY2k9yZ4TQmMGzGQUL5RunwLU0djKUL/xDbDl+VimecQ Hmv/5CWlxfeJr/2N26N3Luo1GoUKpznjGa4HmSPidimDWr1MjBdSRSsRn4WbICHdENCF E0xg== X-Forwarded-Encrypted: i=1; AL+hErH7hGpBM3r8Xfrvewer+uHihsTrPEnifkzdatfp2nPbWcQ4qWBmWq/rMys41RghRkHYbr+Ii9FlDZBr5uM=@vger.kernel.org X-Gm-Message-State: APuU4Z/BugCrRNrZT9y4LPHj8KRTZ2aJsxfevJMcojh67IQgGiXcfILN k0pw92UMuIRqueBlhI2R5nNeuUbQLm1ew1dhFyeYIlDAE2t4DSpS+IvYy89sV526OcMfphnseXP pSWGX08IS4aj7CtSWlYBDsEetXG8EH+HKMk4OEUx7/33tCmbbIE0321u5Qc9VD3WG6Ew= X-Gm-Gg: AYBFou0Tqgb9QCT7bPDo+NOCqGUADllWuU7MQKckQ1lpYN5A+4I0e7aZlke4r9P4rKR 0CxCWezeoina1ulQ549FF04pluIsIPVvE30b/WTcJPkdgTWBrenhaOn5z61dgoA/WLdKxunWFp4 ou6bcU/zQlLIatWDF4mtXhwRkooQV1uwDrN9hAF5NG10pv/QrBMnO/InDxQaUT8ngRoszbe9W4A trMzh4GUQ6UYkvhltA3Ny5iRZJfZj1FSEV5tHdu2CYeFFM5PgNHTgGSKjqFl8eiySpYd7saMQ4i gszJ/4SOTlbBqwUfzjsFj69/DaSJY8SkwCau+PpEyCTNlOM7F1QCIRThOykeaT/EBShjVOW0NFA FQILpZkksoY0yfC3K6oOii4Np2BrHdCey3720krDTiSlCZBwYJ23lN/Ak1R/Skm/8CTvLrwHLSF K5q8SudlFg X-Received: by 2002:a05:693c:8842:b0:369:535f:4d12 with SMTP id 5a478bee46e88-36f729cf093mr3740685eec.3.1793968444550; Fri, 06 Nov 2026 04:34:04 -0800 (PST) X-Received: by 2002:a05:693c:8842:b0:369:535f:4d12 with SMTP id 5a478bee46e88-36f729cf093mr3740627eec.3.1793968443693; Fri, 06 Nov 2026 04:34:03 -0800 (PST) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36faa4b8aacsm6514804eec.23.2026.11.06.04.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 04:34:02 -0800 (PST) From: Mohammad Rafi Shaik Date: Fri, 06 Nov 2026 18:03:07 +0530 Subject: [PATCH v6 v6 8/9] ASoC: qcom: lpass-tx-macro: Add support for Bolero v4.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261106-add_shikra_support-v6-8-2cda302237cc@oss.qualcomm.com> References: <20261106-add_shikra_support-v6-0-2cda302237cc@oss.qualcomm.com> In-Reply-To: <20261106-add_shikra_support-v6-0-2cda302237cc@oss.qualcomm.com> To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: Mohammad Rafi Shaik , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prasad Kumpatla , Sarath Ganapathiraju X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793968394; l=32040; i=mohammad.rafi.shaik@oss.qualcomm.com; s=20260424; h=from:subject:message-id; bh=2M43uIQl1syPx3vEs+PcCbqO8BWy6Amm5MK8I5JUfeg=; b=aiji9JgxYDyMSCxuMdupSIHDQ3/xz8ldL7EACQJH+9KusNgn7zGlWD5/UmEycYv4IsIumum+2 o5YgUgdUMvJCBifBpCgcA48rSBLFNV6I3Hkx+PsveRJvskhr6HzILXL X-Developer-Key: i=mohammad.rafi.shaik@oss.qualcomm.com; a=ed25519; pk=KZedmYgMGYOzuTpLGv56tdrL+pTLDP8pdmfQ91xemiA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA0OSBTYWx0ZWRfX45wA23Fnw+YP 8zMifZJjzPnPQR0oE+fCWq07bI6JpCIsHe+BYnzqDKyraLishVx288IStdL/VfbwQxpKGR6io17 upIscOMVeWI34EWZ34onxcEtUzgOBsbML4dtrLgy6nBT7qbsr46ixs5Y7qXssxwM8JKC4zn3R7F fAx4L5CYdPxlXX9tLKRVVRkNg+0HB6Z8YeW9qUU9Jgdrcxpali4NIX6Hnon1m+vO0LsB65oAm2j 6PflPDN7x+yWUqn8q1FxgiiQSoY3i03J6+3YdH1PYUB570hlCdH52y5O4n5tQitNpDhr1Kf7J3Q IBJy/MQXJH0x5Eb3AOgJhw+55FobXIDMfOocL4Jn+w/N3QQ2yrAtX98zQ0/rGrfnEff+6a8sTZA 4DPm4isiOTRSCyO/Uz4zSUA88HZ676Tu0KTy6kLidIbs/RIeWsDNApe6J0KKfybDXp78PJRkJWK FJGxe07LN5OI6NsCJpA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA0OSBTYWx0ZWRfX/CRbi/ut75QK /D8WsZascMMjshUjR2efvATFjUUdtj/B68GS0Vy/jUaPFQ9xiheWzZ3mQYIEJcd15DswjCKoRmL ipMrQOfRkFWHR9rMNdwGTIyBlO3uugc= X-Proofpoint-ORIG-GUID: AasljuZVGCcdNwq9Ts-h3AAmjbd5ElqL X-Authority-Analysis: v=2.4 cv=GpzXaU1C c=1 sm=1 tr=0 ts=6aedc93e cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=KrMgExgf9dcUfBKOTL4A:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: AasljuZVGCcdNwq9Ts-h3AAmjbd5ElqL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_03,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 malwarescore=0 priorityscore=1501 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060049 From: Prasad Kumpatla Hawi integrates the Bolero v4.0 TX macro. This version extends the existing TX macro register layout with CFG2 port-select registers, per-path CFG2 registers and an ADPT control block. Add the v4.0 register defaults and extend the regmap accessors and maximum register offset only for the v4.0 match data. Use REGCACHE_MAPLE for the TX macro regmap since the register defaults are sparse and the v4.0 layout extends the register range. Bolero v4.0 also needs a different decimator mux enum. Move the common TX DEC widgets out of the shared widget table and register exactly one decimator widget table per version. This avoids duplicate TX DECn MUX DAPM widgets while keeping the v4.0-specific enum and DAPM events. Add the v4.0 SMIC, WSA and port-select mux widgets and routes, and disable the ADPT block before enabling a decimator on v4.0 hardware. Co-developed-by: Sarath Ganapathiraju Signed-off-by: Sarath Ganapathiraju Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-macro-common.h | 1 + sound/soc/codecs/lpass-tx-macro.c | 576 +++++++++++++++++++++++++++++++++- 2 files changed, 565 insertions(+), 12 deletions(-) diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass-macro-common.h index b52665b11e35..707b22a6bda6 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -16,6 +16,7 @@ enum lpass_version { LPASS_VER_9_2_0, LPASS_VER_10_0_0, LPASS_VER_11_0_0, + LPASS_VER_15_0_0, }; enum lpass_codec_version { diff --git a/sound/soc/codecs/lpass-tx-macro.c b/sound/soc/codecs/lpass-tx-macro.c index 6deaaabe43af..6480a6c9032e 100644 --- a/sound/soc/codecs/lpass-tx-macro.c +++ b/sound/soc/codecs/lpass-tx-macro.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -67,6 +68,14 @@ #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134) #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138) #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C) +#define CDC_TX_INP_MUX_ADC_MUX0_CFG2 (0x0140) +#define CDC_TX_INP_MUX_ADC_MUX1_CFG2 (0x0144) +#define CDC_TX_INP_MUX_ADC_MUX2_CFG2 (0x0148) +#define CDC_TX_INP_MUX_ADC_MUX3_CFG2 (0x014C) +#define CDC_TX_INP_MUX_ADC_MUX4_CFG2 (0x0150) +#define CDC_TX_INP_MUX_ADC_MUX5_CFG2 (0x0154) +#define CDC_TX_INP_MUX_ADC_MUX6_CFG2 (0x0158) +#define CDC_TX_INP_MUX_ADC_MUX7_CFG2 (0x015C) #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200) #define CDC_TX_ANC0_MODE_1_CTL (0x0204) #define CDC_TX_ANC0_MODE_2_CTL (0x0208) @@ -108,6 +117,17 @@ #define CDC_TX0_TX_PATH_SEC5 (0x0424) #define CDC_TX0_TX_PATH_SEC6 (0x0428) #define CDC_TX0_TX_PATH_SEC7 (0x042C) +#define CDC_TX0_TX_PATH_CFG2 (0x0430) +#define CDC_TX1_TX_PATH_CFG2 (0x04B0) +#define CDC_TX2_TX_PATH_CFG2 (0x0530) +#define CDC_TX3_TX_PATH_CFG2 (0x05B0) +#define CDC_TX4_TX_PATH_CFG2 (0x0630) +#define CDC_TX5_TX_PATH_CFG2 (0x06B0) +#define CDC_TX6_TX_PATH_CFG2 (0x0730) +#define CDC_TX7_TX_PATH_CFG2 (0x07B0) +#define CDC_ADPT0_ADPT_CTRL (0x0800) +#define CDC_TX_ADPT_CTRL_EN_MASK GENMASK(7, 0) + #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6) #define CDC_TX1_TX_PATH_CTL (0x0480) #define CDC_TX1_TX_PATH_CFG0 (0x0484) @@ -186,7 +206,8 @@ #define CDC_TX7_TX_PATH_SEC4 (0x07A0) #define CDC_TX7_TX_PATH_SEC5 (0x07A4) #define CDC_TX7_TX_PATH_SEC6 (0x07A8) -#define TX_MAX_OFFSET (0x07A8) +#define TX_MAX_OFFSET (CDC_TX7_TX_PATH_SEC6) +#define TX_4_0_MAX_OFFSET (CDC_ADPT0_ADPT_CTRL) #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ @@ -258,6 +279,9 @@ struct hpf_work { struct tx_macro_data { unsigned int flags; unsigned int ver; + bool has_adpt; + const struct snd_soc_dapm_widget *dec_widgets; + size_t dec_widgets_num; const struct snd_soc_dapm_widget *extra_widgets; size_t extra_widgets_num; const struct snd_soc_dapm_route *extra_routes; @@ -434,6 +458,26 @@ static struct reg_default tx_defaults[] = { { CDC_TX7_TX_PATH_SEC6, 0x00}, }; +static const struct reg_default tx_4_0_defaults[] = { + { CDC_TX_INP_MUX_ADC_MUX0_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX1_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX2_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX3_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX4_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX5_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX6_CFG2, 0x00}, + { CDC_TX_INP_MUX_ADC_MUX7_CFG2, 0x00}, + { CDC_TX0_TX_PATH_CFG2, 0x03}, + { CDC_TX1_TX_PATH_CFG2, 0x03}, + { CDC_TX2_TX_PATH_CFG2, 0x03}, + { CDC_TX3_TX_PATH_CFG2, 0x03}, + { CDC_TX4_TX_PATH_CFG2, 0x03}, + { CDC_TX5_TX_PATH_CFG2, 0x03}, + { CDC_TX6_TX_PATH_CFG2, 0x03}, + { CDC_TX7_TX_PATH_CFG2, 0x03}, + { CDC_ADPT0_ADPT_CTRL, 0x00}, +}; + static bool tx_is_volatile_register(struct device *dev, unsigned int reg) { /* Update volatile list for tx/tx macros */ @@ -597,6 +641,32 @@ static bool tx_is_rw_register(struct device *dev, unsigned int reg) return false; } +static bool tx_4_0_is_rw_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case CDC_TX_INP_MUX_ADC_MUX0_CFG2: + case CDC_TX_INP_MUX_ADC_MUX1_CFG2: + case CDC_TX_INP_MUX_ADC_MUX2_CFG2: + case CDC_TX_INP_MUX_ADC_MUX3_CFG2: + case CDC_TX_INP_MUX_ADC_MUX4_CFG2: + case CDC_TX_INP_MUX_ADC_MUX5_CFG2: + case CDC_TX_INP_MUX_ADC_MUX6_CFG2: + case CDC_TX_INP_MUX_ADC_MUX7_CFG2: + case CDC_TX0_TX_PATH_CFG2: + case CDC_TX1_TX_PATH_CFG2: + case CDC_TX2_TX_PATH_CFG2: + case CDC_TX3_TX_PATH_CFG2: + case CDC_TX4_TX_PATH_CFG2: + case CDC_TX5_TX_PATH_CFG2: + case CDC_TX6_TX_PATH_CFG2: + case CDC_TX7_TX_PATH_CFG2: + case CDC_ADPT0_ADPT_CTRL: + return true; + default: + return tx_is_rw_register(dev, reg); + } +} + static const struct regmap_config tx_regmap_config = { .name = "tx_macro", .reg_bits = 16, @@ -604,8 +674,7 @@ static const struct regmap_config tx_regmap_config = { .reg_stride = 4, .cache_type = REGCACHE_MAPLE, .max_register = TX_MAX_OFFSET, - .reg_defaults = tx_defaults, - .num_reg_defaults = ARRAY_SIZE(tx_defaults), + /* .reg_defaults and .num_reg_defaults set in probe() */ .writeable_reg = tx_is_rw_register, .volatile_reg = tx_is_volatile_register, .readable_reg = tx_is_rw_register, @@ -929,6 +998,10 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_PRE_PMU: + /* Disable the ADPT block before enabling the decimator */ + if (tx->data->has_adpt) + snd_soc_component_write_field(component, CDC_ADPT0_ADPT_CTRL, + CDC_TX_ADPT_CTRL_EN_MASK, 0x0); adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator); if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) { adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator); @@ -1456,6 +1529,17 @@ static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { SND_SOC_DAPM_INPUT("TX DMIC6"), SND_SOC_DAPM_INPUT("TX DMIC7"), + SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, + tx_macro_mclk_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, + NULL, 0), +}; + +static const struct snd_soc_dapm_widget tx_macro_dec_dapm_widgets[] = { SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, TX_MACRO_DEC0, 0, &tx_dec0_mux, tx_macro_enable_dec, @@ -1503,14 +1587,6 @@ static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { &tx_dec7_mux, tx_macro_enable_dec, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, - tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0), - - SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, - NULL, 0), }; static const struct snd_soc_dapm_route tx_audio_map[] = { @@ -2027,6 +2103,418 @@ static const struct snd_soc_dapm_route tx_audio_map_v9_2[] = { {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT11"}, }; +static const char * const adc_mux_text_v9_3[] = { + "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1", "RX_SWR_MIC" +}; + +static SOC_ENUM_SINGLE_DECL(tx_dec0_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX0_CFG1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec1_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX1_CFG1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec2_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX2_CFG1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec3_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX3_CFG1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec4_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX4_CFG1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec5_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX5_CFG1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec6_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX6_CFG1, + 0, adc_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_dec7_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX7_CFG1, + 0, adc_mux_text_v9_3); + +static const struct snd_kcontrol_new tx_dec0_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum_v9_3); +static const struct snd_kcontrol_new tx_dec1_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum_v9_3); +static const struct snd_kcontrol_new tx_dec2_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum_v9_3); +static const struct snd_kcontrol_new tx_dec3_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum_v9_3); +static const struct snd_kcontrol_new tx_dec4_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum_v9_3); +static const struct snd_kcontrol_new tx_dec5_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum_v9_3); +static const struct snd_kcontrol_new tx_dec6_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum_v9_3); +static const struct snd_kcontrol_new tx_dec7_mux_v9_3 = + SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum_v9_3); + +static const char * const smic_mux_text_v9_3[] = { + "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", + "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", +}; + +static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX0_CFG0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX1_CFG0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX2_CFG0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX3_CFG0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX4_CFG0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX5_CFG0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX6_CFG0, + 0, smic_mux_text_v9_3); +static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9_3, CDC_TX_INP_MUX_ADC_MUX7_CFG0, + 0, smic_mux_text_v9_3); + +static const struct snd_kcontrol_new tx_smic0_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic0", + tx_smic0_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); +static const struct snd_kcontrol_new tx_smic1_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic1", + tx_smic1_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); +static const struct snd_kcontrol_new tx_smic2_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic2", + tx_smic2_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); +static const struct snd_kcontrol_new tx_smic3_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic3", + tx_smic3_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); +static const struct snd_kcontrol_new tx_smic4_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic4", + tx_smic4_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); +static const struct snd_kcontrol_new tx_smic5_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic5", + tx_smic5_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); +static const struct snd_kcontrol_new tx_smic6_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic6", + tx_smic6_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); +static const struct snd_kcontrol_new tx_smic7_mux_v9_3 = SOC_DAPM_ENUM_EXT("tx_smic7", + tx_smic7_enum_v9_3, snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum); + +static const char * const tx_wsa_mux_text[] = { + "NO_WSA", "WSA1", "WSA2", "WSA3", "WSA4" +}; + +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1, + 4, tx_wsa_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_wsa_mux7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1, + 4, tx_wsa_mux_text); + +static const struct snd_kcontrol_new tx_wsa_mux0_mux = + SOC_DAPM_ENUM("tx_wsa_mux0", tx_wsa_mux0_enum); +static const struct snd_kcontrol_new tx_wsa_mux1_mux = + SOC_DAPM_ENUM("tx_wsa_mux1", tx_wsa_mux1_enum); +static const struct snd_kcontrol_new tx_wsa_mux2_mux = + SOC_DAPM_ENUM("tx_wsa_mux2", tx_wsa_mux2_enum); +static const struct snd_kcontrol_new tx_wsa_mux3_mux = + SOC_DAPM_ENUM("tx_wsa_mux3", tx_wsa_mux3_enum); +static const struct snd_kcontrol_new tx_wsa_mux4_mux = + SOC_DAPM_ENUM("tx_wsa_mux4", tx_wsa_mux4_enum); +static const struct snd_kcontrol_new tx_wsa_mux5_mux = + SOC_DAPM_ENUM("tx_wsa_mux5", tx_wsa_mux5_enum); +static const struct snd_kcontrol_new tx_wsa_mux6_mux = + SOC_DAPM_ENUM("tx_wsa_mux6", tx_wsa_mux6_enum); +static const struct snd_kcontrol_new tx_wsa_mux7_mux = + SOC_DAPM_ENUM("tx_wsa_mux7", tx_wsa_mux7_enum); + +static const char * const tx_psel_mux_text[] = { + "PORT0", "PORT1", "PORT2", "PORT3", "PORT4" +}; + +static SOC_ENUM_SINGLE_DECL(tx_psel_mux0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG2, + 0, tx_psel_mux_text); +static SOC_ENUM_SINGLE_DECL(tx_psel_mux7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG2, + 0, tx_psel_mux_text); + +static const struct snd_kcontrol_new tx_psel_mux0_mux = + SOC_DAPM_ENUM("tx_psel_mux0", tx_psel_mux0_enum); +static const struct snd_kcontrol_new tx_psel_mux1_mux = + SOC_DAPM_ENUM("tx_psel_mux1", tx_psel_mux1_enum); +static const struct snd_kcontrol_new tx_psel_mux2_mux = + SOC_DAPM_ENUM("tx_psel_mux2", tx_psel_mux2_enum); +static const struct snd_kcontrol_new tx_psel_mux3_mux = + SOC_DAPM_ENUM("tx_psel_mux3", tx_psel_mux3_enum); +static const struct snd_kcontrol_new tx_psel_mux4_mux = + SOC_DAPM_ENUM("tx_psel_mux4", tx_psel_mux4_enum); +static const struct snd_kcontrol_new tx_psel_mux5_mux = + SOC_DAPM_ENUM("tx_psel_mux5", tx_psel_mux5_enum); +static const struct snd_kcontrol_new tx_psel_mux6_mux = + SOC_DAPM_ENUM("tx_psel_mux6", tx_psel_mux6_enum); +static const struct snd_kcontrol_new tx_psel_mux7_mux = + SOC_DAPM_ENUM("tx_psel_mux7", tx_psel_mux7_enum); + +static const struct snd_soc_dapm_widget tx_macro_dec_dapm_widgets_v15[] = { + SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, + TX_MACRO_DEC0, 0, + &tx_dec0_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, + TX_MACRO_DEC1, 0, + &tx_dec1_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, + TX_MACRO_DEC2, 0, + &tx_dec2_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, + TX_MACRO_DEC3, 0, + &tx_dec3_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, + TX_MACRO_DEC4, 0, + &tx_dec4_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, + TX_MACRO_DEC5, 0, + &tx_dec5_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, + TX_MACRO_DEC6, 0, + &tx_dec6_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, + TX_MACRO_DEC7, 0, + &tx_dec7_mux_v9_3, tx_macro_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), +}; + +static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v15[] = { + SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9_3), + SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9_3), + + SND_SOC_DAPM_MUX("TX WSA MUX0", SND_SOC_NOPM, 0, 0, &tx_wsa_mux0_mux), + SND_SOC_DAPM_MUX("TX WSA MUX1", SND_SOC_NOPM, 0, 0, &tx_wsa_mux1_mux), + SND_SOC_DAPM_MUX("TX WSA MUX2", SND_SOC_NOPM, 0, 0, &tx_wsa_mux2_mux), + SND_SOC_DAPM_MUX("TX WSA MUX3", SND_SOC_NOPM, 0, 0, &tx_wsa_mux3_mux), + SND_SOC_DAPM_MUX("TX WSA MUX4", SND_SOC_NOPM, 0, 0, &tx_wsa_mux4_mux), + SND_SOC_DAPM_MUX("TX WSA MUX5", SND_SOC_NOPM, 0, 0, &tx_wsa_mux5_mux), + SND_SOC_DAPM_MUX("TX WSA MUX6", SND_SOC_NOPM, 0, 0, &tx_wsa_mux6_mux), + SND_SOC_DAPM_MUX("TX WSA MUX7", SND_SOC_NOPM, 0, 0, &tx_wsa_mux7_mux), + + SND_SOC_DAPM_MUX("TX PORT SEL MUX0", SND_SOC_NOPM, 0, 0, &tx_psel_mux0_mux), + SND_SOC_DAPM_MUX("TX PORT SEL MUX1", SND_SOC_NOPM, 0, 0, &tx_psel_mux1_mux), + SND_SOC_DAPM_MUX("TX PORT SEL MUX2", SND_SOC_NOPM, 0, 0, &tx_psel_mux2_mux), + SND_SOC_DAPM_MUX("TX PORT SEL MUX3", SND_SOC_NOPM, 0, 0, &tx_psel_mux3_mux), + SND_SOC_DAPM_MUX("TX PORT SEL MUX4", SND_SOC_NOPM, 0, 0, &tx_psel_mux4_mux), + SND_SOC_DAPM_MUX("TX PORT SEL MUX5", SND_SOC_NOPM, 0, 0, &tx_psel_mux5_mux), + SND_SOC_DAPM_MUX("TX PORT SEL MUX6", SND_SOC_NOPM, 0, 0, &tx_psel_mux6_mux), + SND_SOC_DAPM_MUX("TX PORT SEL MUX7", SND_SOC_NOPM, 0, 0, &tx_psel_mux7_mux), + + SND_SOC_DAPM_INPUT("TX SWR_INPUT"), +}; + +static const struct snd_soc_dapm_route tx_audio_map_v15[] = { + /* DEC0 */ + {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, + {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX0", "SWR_MIC0", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC1", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC2", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC3", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC4", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC5", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC6", "TX WSA MUX0"}, + {"TX SMIC MUX0", "SWR_MIC7", "TX WSA MUX0"}, + {"TX WSA MUX0", "NO_WSA", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA1", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA2", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA3", "TX PORT SEL MUX0"}, + {"TX WSA MUX0", "WSA4", "TX PORT SEL MUX0"}, + {"TX PORT SEL MUX0", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX0", "PORT4", "TX SWR_INPUT"}, + + /* DEC1 */ + {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, + {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX1", "SWR_MIC0", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC1", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC2", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC3", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC4", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC5", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC6", "TX WSA MUX1"}, + {"TX SMIC MUX1", "SWR_MIC7", "TX WSA MUX1"}, + {"TX WSA MUX1", "NO_WSA", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA1", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA2", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA3", "TX PORT SEL MUX1"}, + {"TX WSA MUX1", "WSA4", "TX PORT SEL MUX1"}, + {"TX PORT SEL MUX1", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX1", "PORT4", "TX SWR_INPUT"}, + + /* DEC2 */ + {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, + {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX2", "SWR_MIC0", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC1", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC2", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC3", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC4", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC5", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC6", "TX WSA MUX2"}, + {"TX SMIC MUX2", "SWR_MIC7", "TX WSA MUX2"}, + {"TX WSA MUX2", "NO_WSA", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA1", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA2", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA3", "TX PORT SEL MUX2"}, + {"TX WSA MUX2", "WSA4", "TX PORT SEL MUX2"}, + {"TX PORT SEL MUX2", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX2", "PORT4", "TX SWR_INPUT"}, + + /* DEC3 */ + {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, + {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX3", "SWR_MIC0", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC1", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC2", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC3", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC4", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC5", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC6", "TX WSA MUX3"}, + {"TX SMIC MUX3", "SWR_MIC7", "TX WSA MUX3"}, + {"TX WSA MUX3", "NO_WSA", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA1", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA2", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA3", "TX PORT SEL MUX3"}, + {"TX WSA MUX3", "WSA4", "TX PORT SEL MUX3"}, + {"TX PORT SEL MUX3", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX3", "PORT4", "TX SWR_INPUT"}, + + /* DEC4 */ + {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, + {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX4", "SWR_MIC0", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC1", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC2", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC3", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC4", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC5", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC6", "TX WSA MUX4"}, + {"TX SMIC MUX4", "SWR_MIC7", "TX WSA MUX4"}, + {"TX WSA MUX4", "NO_WSA", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA1", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA2", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA3", "TX PORT SEL MUX4"}, + {"TX WSA MUX4", "WSA4", "TX PORT SEL MUX4"}, + {"TX PORT SEL MUX4", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX4", "PORT4", "TX SWR_INPUT"}, + + /* DEC5 */ + {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, + {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX5", "SWR_MIC0", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC1", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC2", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC3", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC4", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC5", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC6", "TX WSA MUX5"}, + {"TX SMIC MUX5", "SWR_MIC7", "TX WSA MUX5"}, + {"TX WSA MUX5", "NO_WSA", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA1", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA2", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA3", "TX PORT SEL MUX5"}, + {"TX WSA MUX5", "WSA4", "TX PORT SEL MUX5"}, + {"TX PORT SEL MUX5", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX5", "PORT4", "TX SWR_INPUT"}, + + /* DEC6 */ + {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, + {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX6", "SWR_MIC0", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC1", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC2", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC3", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC4", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC5", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC6", "TX WSA MUX6"}, + {"TX SMIC MUX6", "SWR_MIC7", "TX WSA MUX6"}, + {"TX WSA MUX6", "NO_WSA", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA1", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA2", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA3", "TX PORT SEL MUX6"}, + {"TX WSA MUX6", "WSA4", "TX PORT SEL MUX6"}, + {"TX PORT SEL MUX6", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX6", "PORT4", "TX SWR_INPUT"}, + + /* DEC7 */ + {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, + {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, + {"TX SMIC MUX7", "SWR_MIC0", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC1", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC2", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC3", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC4", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC5", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC6", "TX WSA MUX7"}, + {"TX SMIC MUX7", "SWR_MIC7", "TX WSA MUX7"}, + {"TX WSA MUX7", "NO_WSA", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA1", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA2", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA3", "TX PORT SEL MUX7"}, + {"TX WSA MUX7", "WSA4", "TX PORT SEL MUX7"}, + {"TX PORT SEL MUX7", "PORT0", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT1", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT2", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT3", "TX SWR_INPUT"}, + {"TX PORT SEL MUX7", "PORT4", "TX SWR_INPUT"}, +}; + static const struct snd_kcontrol_new tx_macro_snd_controls[] = { SOC_SINGLE_S8_TLV("TX_DEC0 Volume", CDC_TX0_TX_VOL_CTL, @@ -2085,8 +2573,21 @@ static int tx_macro_component_extend(struct snd_soc_component *comp) { struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(comp); struct tx_macro *tx = snd_soc_component_get_drvdata(comp); + const struct snd_soc_dapm_widget *dec_widgets = tx_macro_dec_dapm_widgets; + size_t dec_widgets_num = ARRAY_SIZE(tx_macro_dec_dapm_widgets); int ret; + if (tx->data->dec_widgets_num) { + dec_widgets = tx->data->dec_widgets; + dec_widgets_num = tx->data->dec_widgets_num; + } + + ret = snd_soc_dapm_new_controls(dapm, dec_widgets, dec_widgets_num); + if (ret) { + dev_err(tx->dev, "failed to add decimator widgets: %d\n", ret); + return ret; + } + if (tx->data->extra_widgets_num) { ret = snd_soc_dapm_new_controls(dapm, tx->data->extra_widgets, tx->data->extra_widgets_num); @@ -2250,6 +2751,9 @@ static int tx_macro_probe(struct platform_device *pdev) struct device_node *np = dev->of_node; struct tx_macro *tx; void __iomem *base; + struct reg_default *reg_defaults __free(kfree) = NULL; + struct regmap_config *reg_config __free(kfree) = NULL; + size_t def_count; int ret, reg; tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL); @@ -2304,7 +2808,40 @@ static int tx_macro_probe(struct platform_device *pdev) } } - tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); + reg_config = kmemdup(&tx_regmap_config, sizeof(*reg_config), GFP_KERNEL); + if (!reg_config) { + ret = -ENOMEM; + goto err; + } + + reg_config->reg_defaults = tx_defaults; + reg_config->num_reg_defaults = ARRAY_SIZE(tx_defaults); + + switch (tx->data->ver) { + case LPASS_VER_15_0_0: + def_count = ARRAY_SIZE(tx_defaults) + ARRAY_SIZE(tx_4_0_defaults); + reg_defaults = kmalloc_objs(*reg_defaults, def_count); + if (!reg_defaults) { + ret = -ENOMEM; + goto err; + } + + memcpy(®_defaults[0], tx_defaults, sizeof(tx_defaults)); + memcpy(®_defaults[ARRAY_SIZE(tx_defaults)], + tx_4_0_defaults, sizeof(tx_4_0_defaults)); + regcache_sort_defaults(reg_defaults, def_count); + + reg_config->max_register = TX_4_0_MAX_OFFSET; + reg_config->reg_defaults = reg_defaults; + reg_config->num_reg_defaults = def_count; + reg_config->writeable_reg = tx_4_0_is_rw_register; + reg_config->readable_reg = tx_4_0_is_rw_register; + break; + default: + break; + } + + tx->regmap = devm_regmap_init_mmio(dev, base, reg_config); if (IS_ERR(tx->regmap)) { ret = PTR_ERR(tx->regmap); goto err; @@ -2477,6 +3014,18 @@ static const struct tx_macro_data lpass_ver_11 = { .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2), }; +static const struct tx_macro_data lpass_ver_15 = { + .flags = LPASS_MACRO_FLAG_RESET_SWR, + .ver = LPASS_VER_15_0_0, + .has_adpt = true, + .dec_widgets = tx_macro_dec_dapm_widgets_v15, + .dec_widgets_num = ARRAY_SIZE(tx_macro_dec_dapm_widgets_v15), + .extra_widgets = tx_macro_dapm_widgets_v15, + .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v15), + .extra_routes = tx_audio_map_v15, + .extra_routes_num = ARRAY_SIZE(tx_audio_map_v15), +}; + static const struct of_device_id tx_macro_dt_match[] = { { /* @@ -2499,6 +3048,9 @@ static const struct of_device_id tx_macro_dt_match[] = { }, { .compatible = "qcom,sm8550-lpass-tx-macro", .data = &lpass_ver_11, + }, { + .compatible = "qcom,hawi-lpass-tx-macro", + .data = &lpass_ver_15, }, { .compatible = "qcom,sc8280xp-lpass-tx-macro", /* -- 2.34.1