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Fri, 6 Nov 2026 16:08:14 +0000 (GMT) Received: from a46lp73.lnxne.boe (unknown [9.87.84.240]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 6 Nov 2026 16:08:14 +0000 (GMT) From: Steffen Eiden Date: Fri, 06 Nov 2026 17:07:36 +0100 Subject: [PATCH v3 03/23] arm64: sysreg: Convert OSLSR to automatic register generation X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261106-sysreg-v3-3-75e95980fb10@linux.ibm.com> References: <20261106-sysreg-v3-0-75e95980fb10@linux.ibm.com> In-Reply-To: <20261106-sysreg-v3-0-75e95980fb10@linux.ibm.com> To: Marc Zyngier , Oliver Upton , Fuad Tabba , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Andreas Grapentin , Christian Borntraeger , Janosch Frank , Claudio Imbrenda , David Hildenbrand , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Sven Schnelle , Friedrich Welter , Gautam Gala , Hariharan Mari , Hendrik Brueckner , Nico Boehr , Ulrich Weigand , Arnd Bergmann , Paolo Bonzini Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-s390@vger.kernel.org, Steffen Eiden X-Mailer: b4 0.14.3 X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA2MiBTYWx0ZWRfXx7H/w9GaMmvC wgKjs+HR7dhAyHENO+GdQFOat5SREYxDz9O5rPqdwCgFNuFUGnlTCdSg1r80ZsnRxznEj0twbYp cko3wZaAtPcfzs/r952L+3LIi8VcZB0= X-Proofpoint-GUID: xFcc7uGqZ-HYK0UJbpgCHve9C9pcjYKs X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA2MiBTYWx0ZWRfX5jg/b7IN7rGs faYNdYhVC4YQCKnxMBn23kpjHTub3g22+J2QL3X5MXWz3VneOJapiOCQV7lNc6QFOo4/Ph1tzbP 9cbD5+7a5ucrgFm4PfxPCgT9C8CfFtl3YEJpYtWofPffVMPOYXBR/orXBsTzhGd1LOk3ZtJXGXc 5PE62NwDej8l2gKLUlfqa8Zre3LB4F4zM1dCGTFjd7iby1L1agu+jycE+fQxbf6hBZB7IRgluL7 SQEQhaLXlZUu7mHf8Ru+1UChX4cwPJIHSd9KQMeu3s5nm1hqfJKiraSPjUOzU6ZtOmpg9eLNJDr Q8IZRYU9+elZBg5Rm95mmlBsWIvhv5ghtEOWW2u65BedwPyxmgAVA7jv7bzYOXLEcbL4iuCH3Xr Han6K9p2CgVLctxtkwaixMe+Dx9xc/STC4bwTGAchGxxzDMPm41CUfjgBc6FAm0cbXCgR2V82wY KsizHyymRZh6vmhxXFA== X-Proofpoint-ORIG-GUID: xFcc7uGqZ-HYK0UJbpgCHve9C9pcjYKs X-Authority-Analysis: v=2.4 cv=CY+dd7rl c=1 sm=1 tr=0 ts=6aedfb73 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8 a=uoKN2WSkVIwsLX3wBB8A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_05,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060062 Convert OSLSR to automatic register generation as per DDI0601. As OSLSR_OLSM is a composite field using bit 0 and bit 3 the combined values are still defined manually. While at it rename OSLSR_EL1_OSLM_IMPLEMENTED to OSLSR_EL1_OSLM_IMP to be consistent with the rest of the system register values. No functional changes. Co-developed-by: Andreas Grapentin Signed-off-by: Andreas Grapentin Signed-off-by: Steffen Eiden --- arch/arm64/include/asm/sysreg.h | 12 +++++++----- arch/arm64/kvm/sys_regs.c | 2 +- arch/arm64/tools/sysreg | 14 ++++++++++++++ 3 files changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e3b60ee03023..2ec9ba9cd896 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -186,11 +186,13 @@ #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) -#define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) -#define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0)) -#define OSLSR_EL1_OSLM_NI 0 -#define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3) -#define OSLSR_EL1_OSLK BIT(1) +#define OSLSR_EL1_OSLM_MASK (OSLSR_EL1_OSLM0_MASK | OSLSR_EL1_OSLM1_MASK) +#define OSLSR_EL1_OSLM_NI \ + ((OSLSR_EL1_OSLM1_NI << OSLSR_EL1_OSLM1_SHIFT) | \ + (OSLSR_EL1_OSLM0_VAL_0 << OSLSR_EL1_OSLM0_SHIFT)) +#define OSLSR_EL1_OSLM_IMP \ + ((OSLSR_EL1_OSLM1_IMP << OSLSR_EL1_OSLM1_SHIFT) | \ + (OSLSR_EL1_OSLM0_VAL_0 << OSLSR_EL1_OSLM0_SHIFT)) #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 2b28b929f9f3..8c91de6a4097 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3309,7 +3309,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 }, { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1, - OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, }, + OSLSR_EL1_OSLM_IMP, .set_user = set_oslsr_el1, }, { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 997c62ab72e6..5d38f115bac1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -122,6 +122,20 @@ Res0 63:1 Field 0 OSLK EndSysreg +Sysreg OSLSR_EL1 2 0 1 1 4 +Res0 63:4 +UnsignedEnum 3 OSLM1 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 2 nTT +EndEnum +Field 1 OSLK +UnsignedEnum 0 OSLM0 + 0b0 VAL_0 +EndEnum +EndSysreg + Sysreg SPMACCESSR_EL1 2 0 9 13 3 UnsignedEnum 63:62 P31 0b00 TRAP_RW -- 2.56.0