[PATCH v2 0/8] drm/msm, media: define the UBWC buffer layout

[Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>]

The layout of UBWC buffers (DRM_FORMAT_MOD_QCOM_COMPRESSED, V4L2 QC08C
and QC10C) has never been written down. The V4L2 formats are documented
as opaque with four or eight planes, the DRM modifier as "macrotiles".
In practice the video decoders, the GPU and the display controller
exchange these buffers, so each side has to reverse-engineer the layout
from the other drivers. Nicolas Dufresne asked for a contract to know
what the V4L2 plugins have to compute when passing decoded frames to
DRM.

Note that patch 2 changes what P010 with DRM_FORMAT_MOD_QCOM_COMPRESSED
means: it used to be set up for P030 (TP10).

Mesa 26.3-rc rounds the NV12 chroma size down for odd sizes; that is
being fixed on the Mesa side, before the layout reaches a release.

Tested by decoding a clip and scanning the frame out with the layout
documented here: QC08C as NV12 on RB5 (Iris), QC10C as P030 on RB3
(Venus) and on RB3 Gen2 (Iris, gen2 firmware). Each frame is identical
to the same frame decoded to linear NV12 or P010. Compressed P010 was
tested on RB3 Gen2 with a frame written by turnip, with P010 support
that is not merged yet.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Changes in v2:
- Described the compressed 10-bit format, P030 (TP10), as P030 instead
  of P010, compressed only, as the SSPP can't fetch linear P030; gave
  P010 a UBWC entry with 16-bit samples (Sashiko, Robert, Rob)
- Documented P030 next to the 16-bit P010 for QCOM_COMPRESSED, mapped
  QC10C to P030
- Explained how the meaning of compressed P010 changed and why
- Venus: dropped DRM import as the reason for the stride fix
- Link to v1: https://patch.msgid.link/20261104-ubwc-format-docs-v1-0-389044012b4e@oss.qualcomm.com

---
Dmitry Baryshkov (8):
      drm/msm/dpu: fix the comment on the RGB UBWC plane count
      drm/msm: separate compressed P010 and P030 (TP10)
      drm/msm: move the UBWC plane size calculation out of DPU
      drm/msm: check UBWC framebuffers against their layout
      drm/fourcc: describe the Qualcomm UBWC layout
      media: docs: pixfmt-reserved: describe the QC08C and QC10C layout
      media: venus: report the QC10C data stride
      media: qcom: iris: describe QC10C as P030 (TP10)

 .../userspace-api/media/v4l/pixfmt-reserved.rst    |  64 ++++++++++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c        |  84 +--------------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c          |   4 +-
 drivers/gpu/drm/msm/disp/mdp_format.c              | 113 ++++++++++++++++++++-
 drivers/gpu/drm/msm/msm_drv.h                      |   3 +
 drivers/gpu/drm/msm/msm_fb.c                       |  39 ++++++-
 drivers/media/platform/qcom/iris/iris_buffer.c     |   2 +-
 drivers/media/platform/qcom/venus/vdec.c           |   5 +-
 include/uapi/drm/drm_fourcc.h                      |  64 ++++++++++--
 10 files changed, 271 insertions(+), 108 deletions(-)
---
base-commit: f1ac44c32cba88ad65dcecd4a279661d14e93651
change-id: 20261027-ubwc-format-docs-7942079e1472

Best regards,
--  
With best wishes
Dmitry