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[2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5c003055a5csm382747e87.13.2026.11.06.05.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 05:44:35 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 06 Nov 2026 15:44:08 +0200 Subject: [PATCH v2 2/8] drm/msm: separate compressed P010 and P030 (TP10) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261106-ubwc-format-docs-v2-2-82949f88f030@oss.qualcomm.com> References: <20261106-ubwc-format-docs-v2-0-82949f88f030@oss.qualcomm.com> In-Reply-To: <20261106-ubwc-format-docs-v2-0-82949f88f030@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Mauro Carvalho Chehab , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , linux-media@vger.kernel.org, Nicolas Dufresne , Vikash Garodia , Dikshita Agarwal , Robert Mader , Neil Armstrong X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3944; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=KC7RvkMVOgn+4H42iwyDdp1mol1keZJGBSWmjNCy+fo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBq7dmx/XJ3HXoJCOTo/Rx/s76+HuJ9CHm0wd2J9 drWRDWw3IuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCau3ZsQAKCRCLPIo+Aiko 1bpaB/9BVzsaVMl5o6civqjjKYdgXyX/hWDiKPEk7ycyeUP+lqIFAVpA3iAeJK371V0PdI+pFJD URgYhFm8fp69l22JEMwuODGNgDubRyJo0gprS0L0RQ/yR+y2do3NvLq0RnB/P+Rp8MiXhAqj9qN JTRe9Cn/uR94bQ6XDEtJPkg602QP6VSVqBVfsajUo3VJ1dneHctp9WTBRhQs5A82gPWsIbt0Y7U SVF3+Dm3JZpX//2A4PNOOs6o7eUutmGdTt0WRHgyiCKG/9v6DGrh4xyi9qmiTy29CFCjFEXgsF4 FsdWDbNhz+E0n7cnMVP36trbhsXZXjwQDXyRVr87ytLXtAKc X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: DkXJfi1BDv8L5PJ9ZupJUjB3PrFPC37R X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDA1NCBTYWx0ZWRfX4TyO3aEmayjr uHEZziopwRsMB2KwG5emDFIWJGmDjzzrp8s9B/+JjH1UGo1pXrB3mdV/Evlx6+L9rhCkRO9pOQR fHt8ywCHeQfJ9mTTZGcQtPJmz6edYUk= X-Authority-Analysis: v=2.4 cv=e7WT2qp/ c=1 sm=1 tr=0 ts=6aedd9c5 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=fSef4fKgGNmnkmXS94sA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDA1NCBTYWx0ZWRfX8Awy/yDH4kaw pvIJYbccwt3m/Xya5Bn6XGf3FgA+eOKQaJcy1Xb12Rt4N7P/FE7QZu6CvgQHVPbOFE51DzN/smZ qwVI3Y16xWqkO3mETLEZehz4X/rEcdNJ/9+EjlAhKwtKvxzNpkJYSME3fuqIGLPP/qmySgJwtQu 7qqwzSLgyI9+KttaWmoDq4cDy+WUC758X1owWZuypk5zsqKzC7ECRGi2Dhf0oXvYx3UeU91F2oh Uxjg6JGCUiqJ4RMNMOYIxeBmCcOc5P0s06sZKi+pjq7BdQs3LJ5INCsrO4HcdEm3dXyZ5UsOfKN Gz6/PxFR9DBzRcJoLMjpXX7LR4wx5wDCLf9pq5hh3z7Ljn905j/zxnn9/FFf6LoC4CpuxjMXcip ByH7XKVEhQjl37uIryTEhJ7mL4+dWgZ4MpdDnN/YQpweaYqNPlZunVKQzAcDX7PxY3V6W4NvHW2 a9Uh65iGuHHp0LfiKRw== X-Proofpoint-ORIG-GUID: DkXJfi1BDv8L5PJ9ZupJUjB3PrFPC37R X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_03,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060054 The UBWC entry for DRM_FORMAT_P010 is set up for P030 (TP10), three 10-bit samples in each 32-bit word, the layout the video decoders produce for QC10C. It doesn't match P010: compressed P010, as the GPU writes it, keeps 16-bit samples and is scanned out as garbage. Use DRM_FORMAT_P030 for that entry, compressed only, as the SSPP can't fetch linear P030, and give P010 its own UBWC entry with 16-bit samples. This changes what compressed P010 means. Nothing is known to depend on the old meaning: Mesa and minigbm never allocate it, the vendor stack uses its own modifier bits, and the only user found is a draft GStreamer merge request. Fixes: f07c9946cc1a ("drm/msm/dpu: Add support for P010 format") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +++- drivers/gpu/drm/msm/disp/mdp_format.c | 13 +++++++++---- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 107150a8553f..f755c0d57abe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -173,6 +173,7 @@ static const uint32_t plane_formats_yuv[] = { DRM_FORMAT_BGRX4444, DRM_FORMAT_P010, + DRM_FORMAT_P030, DRM_FORMAT_NV12, DRM_FORMAT_NV21, DRM_FORMAT_NV16, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 1a471cdf767b..09146023d13e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -68,6 +68,7 @@ static const uint32_t qcom_compressed_supported_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_P010, + DRM_FORMAT_P030, }; /* @@ -1779,8 +1780,9 @@ static bool dpu_plane_format_mod_supported(struct drm_plane *plane, struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); bool has_no_ubwc = (dpu_kms->mdss->ubwc_enc_version == 0); + /* the SSPP can only fetch P030 compressed */ if (modifier == DRM_FORMAT_MOD_LINEAR) - return true; + return format != DRM_FORMAT_P030; if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED && !has_no_ubwc) return dpu_find_format(format, qcom_compressed_supported_formats, diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c index 33da569eae5e..2712a73e5783 100644 --- a/drivers/gpu/drm/msm/disp/mdp_format.c +++ b/drivers/gpu/drm/msm/disp/mdp_format.c @@ -298,8 +298,7 @@ static struct csc_cfg csc_convert[CSC_MAX] = { .unpack_count = 2, \ .bpp = 2, \ .fetch_mode = MDP_FETCH_UBWC, \ - .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \ - MSM_FORMAT_FLAG_YUV | \ + .flags = MSM_FORMAT_FLAG_YUV | \ MSM_FORMAT_FLAG_COMPRESSED | flg, \ .num_planes = 4, \ .tile_height = th \ @@ -606,13 +605,19 @@ static const struct msm_format mdp_formats_ubwc[] = { PSEUDO_YUV_FMT_TILED(NV12, BPC8, BPC8, BPC8, C1_B_Cb, C2_R_Cr, - CHROMA_420, 0, + CHROMA_420, MSM_FORMAT_FLAG_UNPACK_TIGHT, MDP_TILE_HEIGHT_NV12), + PSEUDO_YUV_FMT_TILED(P030, + BPC8, BPC8, BPC8, + C1_B_Cb, C2_R_Cr, + CHROMA_420, MSM_FORMAT_FLAG_UNPACK_TIGHT | MSM_FORMAT_FLAG_DX, + MDP_TILE_HEIGHT_UBWC), + PSEUDO_YUV_FMT_TILED(P010, BPC8, BPC8, BPC8, C1_B_Cb, C2_R_Cr, - CHROMA_420, MSM_FORMAT_FLAG_DX, + CHROMA_420, MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | MSM_FORMAT_FLAG_DX, MDP_TILE_HEIGHT_UBWC), }; -- 2.47.3